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Anatol URSU

MONTPELLIER

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Montpellier ainsi que le résultat des européennes dans l'Hérault.

En résumé

Mes compétences :
JavaScript, Python, Perl, Tcl
Java (JDK, Spring, Camel, GWT)
C/C++, MS Visual C++, GNU gcc/g++
VHDL, Verilog
Electronic design automation (EDA)
Formal Verification

Entreprises

  • Lycée Jean Mermoz, Montpellier, France - Teacher on Information Systems

    2015 - 2015 Teacher on Information Systems

  • Cortus SAS, Montpellier, France - R&D Engineer

    2014 - 2014 Optimisation of a microprocessor unit.

  • Qualtera, Montpellier, France - Software developer

    2011 - 2013 R&D software developer. The project (SiliconDash) was the development and the testing of a complex application for high-volume semiconductor data (fables, foundry, IDM) analysis. The main development tasks were the implementation and testing of statistical analysis algorithms.

  • Synopsys, Montpellier. France - Software developer

    2008 - 2009 R&D software developer of EDA (Electronic Design Automation) tools for the synthesis, the verification and the testing of FPGA/ASIC designs. The main tasks were the development of the tools Synplify, Identify, Certify, etc. Synposys acquired Synplicity in May 2008. See my activities in Synplicity Inc below

  • Synplicity, Montpellier, France - Software developer

    2001 - 2008 R&D software developer of EDA (Electronic Design Automation) tools for the synthesis, the verification and the testing of FPGA/ASIC designs. The main projects were the tools Synplify, Identify, Certify, etc.
    The main development tasks:
    • an equivalence checking tool for ASIC and FPGA designs. In implementing this tool I was mainly involved in a boolean matching technique that extracts equivalent points in two designs. I have good experience in using BDD, AIG and SAT solvers code in equivalence checking and optimization techniques;
    • a tool to insert debugging modules in FPGA designs for RTL debugging with Indentify tool (RTL debugging tool using FPGA hardware emulation and HDL simulation),
    • a RAM extraction tool for ASIC designs at RTL level for Synplify DSP tool,
    • a TCL interface for a schematic netlist editor for Certify, which is an FPGA-based ASIC prototyping tool,
    • a design for test (DFT) tool for scan insertion in ASIC designs,
    • a power estimation technique for ASIC designs.

  • Technical University of Moldavia (Moldavia - former USSR republic) - Computer Science Teacher

    1984 - 2001 Teaching object oriented programming, concurrent programming, network programming, communication interfaces (buses), network protocols, information systems design, information technologies, operating systems, etc. The research projects: formal verification using temporal logic.

Formations

Pas de formation renseignée

Réseau

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