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Areski MAKLOUF

Paris-13E-Arrondissement

En résumé

- Project leader & Senior Designer digital ASIC, FPGA.
- Designer FPGA MICROSEMI, XILINX VIRTEX-6, ALTERA QUARTUS.
- Designer ASIC SoC FRONT-END, BACK-END.
- Specification, development, verification ASIC, FPGA.
- Hardware Platform Architect for SMARTPHONE & TABLET application.
- Processor architectures ARM.
- Knowledge standard DO-254.

Mes compétences :
ASIC
FPGA
VHDL
Synthèse
Verilog

Entreprises

  • Groupe SII - Designer FPGA

    Paris-13E-Arrondissement 2015 - maintenant - FPGA specification and design at Airbus Defense and Space

  • Groupe Bull - Senior digital ASIC designer

    Les Clayes-sous-Bois 2012 - 2015 Consulting at BULL

  • ST-ERICSSON - Hardware Platform Architect

    2009 - 2012 - Smartphone, Tablet application

  • STMICROELECTRONICS - Hardware Platform Architecte

    2005 - 2009 - Application Processor Platform

  • STMICROELECTRONICS - Digital SoC Architect

    2002 - 2005 - ASIC Modem Baseband

  • ALCATEL MICROELECTRONICS - Digital ASIC Team Leader

    2001 - 2002

  • THALES MICROELECTRONICS - ASIC Digital Project Leader

    Courbevoie 1998 - 2001

  • SOREP - Consulting Design ASIC/FPGA

    1993 - 1998 - ALCATEL ABS, Paris, 1997-1998
    - SOGITEC, DASSAULT AVIATION, Suresnes, 1996-1997
    - SAGEM/SAT, Paris, 1994-1996
    - ALCATEL ABS, Paris, 1993-1994

Formations

Réseau

Annuaire des membres :