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Ayman REGAIEG

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En résumé

FPGA Design and verification engineer, perform the whole FPGA Projects life cycle from the specification to the physical verification (For airborne hardware electronics and following the standard DO-254).

Technical skills:
- VHDL/Verilog, C/C++, Assembler, Tcl/TK Script.

- FPGA(Xilinx, Altera, Actel), ASIC, µC, ARINC429 RX/TX, SPI Master/Slave, Avalon-MM/ST Bus, BFM, SDA RX/TX, APB bus, EBI bus, CPXD(Common Pressure Transducer), DAC, ADC, GPIO, RTC(Real Time Clock), Watchdog, WFM(Weight Flow Meter), PMA(Permanent Magnet Alternator), DDR3 SDRAM memory Controller (ATERA), UART RX/TX, I2C, Coder/Decoder Reed Solomon, MRAM memory controller, Flash NOR memory controller, NIOS II processor.

- Modelsim/QuestaSim, Quartus(ALTERA)/Eclipse for NIOS, Libero(ACTEL), ISE(Xilinx), Sinplify Pro, Labview, Matlab-sumilink, Microsoft Visual studio, CVS, FileZilla, BugZilla, Reqtify, HDL designer, Doxygen, Microsoft Office (Word, Excel, Visio, MS-project).

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** Design activities:
- Specification, design architecture documents and Requirements traceability.
- RTL code elaboration using VHDL/verilog langage (clock domains management, SEU protection).
- Unit tests to validate the design blocs and fonctionnalities (Protocols, IPs) using software/hardware design methodology (VHDL/C).
- RTL code Synthesis, Timings Analysis(STA), SEU Analysis and Bitstream generation/integration.
- RTL code optimization (Logics/Timings).

** Verifcation activities:
- Virtual and physical Tests procedures document.
- Custom and Automated virtual verifcation environments (VHDL/Verilog, Tcl Script, C/C++).
- Software tests for physical verification (µC, Processors).
- Code coverage and functional verification results analysis.
- Bugs tracking and analysing using generated test logs and Problems Reporting.
- Tests results documents.

Mes compétences :
FPGA
VHDL
Développement RTL
Verification formelle
DO-254
Tcl/Tk
DDR3
Xilinx
Actel
Altera

Entreprises

  • HCELL-Engineering - Senior FPGA Engineer

    2010 - maintenant Main activities : FPGA design, verification (RTL, VHDL) and documents elaboration.

    Projects:

    - Electrical Power control and analysis FPGAs: FPGAs Design and verification using Xilinx Spartan6 technology (UART, I2C, SPI, ADC, Data management, Clocks domains management, Complex calculation, sinus values checking, three-phases signals analysis).

    - RTL Design and virtual and physical verification of the following IPs using StratixV and Arria10 technologies(Intouch interface for Airplane Dashboard, Project in progress):
    ** MRAM memory controller with Quad/Single SPI protocol(EVERSPIN MR20H40 / MR25H40 and MR10Q010).
    ** Serial Flash NOR memory controller (SPANSION S25FS-S Family).
    ** DDR3 memory controller with error correction "Reed Solomon" (8Gb DDR3 micron memory:x16 TwinDie DDR3L SDRAM).

    - Update the NIOS II processor with D$, MPU, MMU and ECC modules and performing its virtual and physical verification.

    - Update the RTL code of the BRIDGE GENERIC FPGA and perfom its verification according to standard DO-254 DAL A using Actel technology (ProAsic A3P600/A3P1000).

    - Migration from DAL C to DAL A in DO-254 of the LGMS component (Landing Gear Monitoring System for AIRBUS A350 XWB) using Actel technology (ProASIC A3P600).

    - From specification to the project certification according to the standard DO-254: RTL Design and verification of 5 FPGAs to implement in the LGBSCU calculator of the aircraft LJ85 (LJ200 Project) according to the standard DO-254 DAL A using Actel technology (ProAsic A3P600/A3P1000).

Formations

  • National Engineering School Of Sfax TUNISIA (Sfax)

    Sfax 2007 - 2009 Engineer's degree, Electrical, Electronics and New Technologies

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