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Benoit CHAUDON

AIX-EN-PROVENCE

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Aix-en-Provence ainsi que le résultat des européennes dans les Bouches-du-Rhône.

En résumé

INGENIEUR ELECTRONICIEN/ELECTROTECHNICIEN
19 ANS D’EXPERIENCE
CONCEPTION/VALIDATION DE CIRCUITS INTEGRES
MANAGEMENT DE PROJETS
ORGANISE, FIABLE, TRAVAIL EN EQUIPE GOÛT POUR LE SERVICE CLIENT

Mes compétences :
CMOS
SUPPLY MONITORING POWER MANAGMENT
IOs, bandgap, comparators, buffers , low power
LVDS
Cadence, Eldo, Spice, Verilog
Signal Integrity analysis
Quality Assurance
Failure Analysis
Layout : matching, DFM, Antenna, DRC, LVS ....

Entreprises

  • CNAM-PACA - Etudiant cours du soir chargé d'affaires en électricité

    2015 - maintenant

  • INVIA - Layout Engineer

    2015 - 2015 Layout Testchip for Flash Product in UMC 65nm technology

  • Maya-Technologies - Design leader

    Seyssins 2014 - 2014 Design Leader Maya-Technologies ADC 14bits CMOS 0.35 µm
    * Team management, planning, writing of specifications
    * Design of sub-blocs.

  • Maya-Technologies - Analog design layout engineer

    Seyssins 2006 - 2013 Analog design layout engineer for STM8 and STM32 microcontrollers' families ST
    Microelectronics Rousset : Consultant for Maya-Technologies
    * Used technologies: CMOS 0.35µm, 0.18µm, 90nm, 40nm. ;
    * Low Power Bandgap, temperature sensor, fast startup, ESD immunity, low mismatch) ;
    * Low power buffers, comparators, latched comparator, rail to rail comparator. ;
    * Power On Reset, power management top simulation (with power switch) ;
    * Supply monitoring by switched capacitor ;
    * Touch sensing module application (Zero Crossing Comparator) ;
    * Validation : internal RC, power supply monitoring, product (micro-controller), Verilog model.

    Microcontrollers Quality Assurance & Reliability ST Microelectronics Rousset
    Consultant for Maya-Technologies
    * Failure Analysis Request for automotive customer for STM8 and SMT32 microcontroller's families. ;
    * Qualification of new products.

  • psi-electronics - Analog designer

    2005 - 2006 ADC evaluation 12bits 5MS for CNET Toulouse : Consultant for psi-electronics
    *concept review
    *Writing an entire design flow of an ADC 12bits 5MS ;
    *Design, layout, validation, production, analysis of different design solutions.

  • Texas Instruments - Design engineer

    Villeneuve-Loubet 2005 - 2005 Electrical and validation design engineer Texas Instruments
    Consultant for psi-electronics
    * Signal Integrity analysis on DDR interface to evaluate electrical and timing specifications including all parasitic effects such as coupling inductances, resistances, board routing (bond wire on signal and power pads, PCB line, IR drop, eye diagram ...)
    * Modeling of transmission lines on different die/package/PCB levels ;
    * Top level validation by taking into account IOs ring.

    Analog design layout and top validation engineer ON Semi-Conductor
    Consultant for psi-electronics
    * Used technology : TSMC 0.25µm ;
    * Current mode buck switching converter implemented with switched capacitor analog blocks. ;
    * Block level and topcell simulations, testchip layout. ;
    * Input voltage range : 0.8V-7V. Output voltage range : 0.6V-Vin (programmable. Output current
    600mA. Inductor : 1µH. Frequency : 625Khz

  • Texas Instruments - Analog design layout engineer

    Villeneuve-Loubet 2002 - 2004 Consultant for psi-electronics
    * Used technologies : CMOS 0.18um/0.12um ;
    * Analog IOs librairies, Tactical IOs in technology ``Extended Drain'' ;
    * SubLVDS input @208Mhz and 416Mhz. ;
    * Top level validation for CCPV2 application: data transmission/reception for a laptop camera.

  • Analog - Design & layout engineer

    2000 - 2002 Analog design and layout engineer ST Microelectronics Grenoble & Rousset
    Consultant for psi-electronics
    * Analog Back End for Wireless Applications in BiCMOS 0.35um technology. ;
    * VCO, PLL, Bias, Comparator, divider: consumption optimization. ;
    * I/Os library design and layout : (CMOS 0.12um) NORM LVTTL (180MHz), SSTL (300Mhz). ;
    * Code generation versus temperature. ;
    * PLL 80-160MHz design and portage in technology CMOS 0.18um.

  • Texas Instruments - Analog design layout engineer

    Villeneuve-Loubet 1997 - 2000 Consultant for Brime Technologies
    * LVDS 450Mhz: design, layout (gate array), characterization ;
    * Clock recovery 700MHz : design, place & route, Serial/parallel & parallel/serial converters ;
    * Digital cells library optimization (design & layout) for 1.25Gbits chip implementation. ;
    * 2 months in Dallas : place and route, flow setup, engineers trainings. ;
    * I/Os & digital libraries design layout, characterization, testchip design

  • THOMSON CSF - Electrical and developer & engineer

    1995 - 1996 Electrical and developer & engineer for a Digital Design Kit for Mentor Graphics :



    EDUCATION

Formations

Pas de formation renseignée

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