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Atrenta France
- Solutions Architect
2013 - 2015
Working in close cooperation with Atrenta R&D and Marketing organizations to strengthen product offer and positioning in the following domains:
+ RTL restructuring for SoC realization & cost reduction
+ Physical aware Power Estimation at RTL level
+ Usability & ergonomics of user interface
Qualification of RTL Power estimation platform on various designs, in cooperation with LETI laboratory (Part of CEA organization)
Articulating a Pre-RTL SoC assembly flow down to qualified RTL for implementation
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STMicroelectronics
- CAD and Design Methodology Director
2005 - 2013
Managing a team of 30 engineers located in EU, US and India, supporting the UPD R&D HW design community (600+ designers worldwide).
+ Responsible for CAD budget (20M$) for Unified Platform Division of ST
+ Managing design flow definition and deployment, main achievements being:
. 2002 Introduction of automated IP development Flow, along with embedded quality checkers
. 2005 SoC Gate level prototyping and restructuring, physical timing budgeting,
. 2007 IPXACT based SoC RTL assembly flow
. 2008 Pseudo-flat chip assembly and timing convergence
. 2011 RTL level prototyping and partitioning, RTL restructuring
+ Project Manager for cost reductions programs:
With a design team located in India, redesign of high-runners circuits (from RTL to GDS) to improve the margin and compensate ASP erosion (technology migration, synthesis optimization, denser P&R etc ...).
+ Forward looking cooperation with main CAD vendors R&D (Synopsys, Cadence, Mentor,Atrenta, Apache), setting cooperation programs to tune CAD solutions to the ST needs. Specification of features for the next generation of tools to sustain the vision of flow evolution.
+ Selecting point tools from startups, helping them to grow within ST (Azuro, CWS, SatinIP, Proxymus, Bluespec, OrbitIO, and Sierra)
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STMicroelectronics
- Design Operations Manager
2003 - 2005
Coordination of design execution of set-top-box SoCs using submicron Cmos processes (130nm * 45nm)
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Thomson Consumer Electronic Components
- CAD & Libraries Manager
1993 - 2002
Head of a 9 engineer team, supporting 50 designers in EU and 10 designers in US
+ Definition, development & support of the Digital design flow for ASIC and full custom designs
. ASIC flow : Compass, Synopsys Synthesis, Zycad emulation, Cadence P&R
. Full custom flow: Cadence Synopsys, Epic
+ Setting up of a comprehensive design support solution:
. Expertise in CMOS design (0.7um, 0.5um, 0.35um)
. Project dedicated libraries to optimize density and/or speed
. Dedicated custom blocks design (embedded DRAMS, Viterbi Decoder, CPU core,
Systolic arrays...)
. Built up of IC debug expertise (EBeam, IC repair technologies)
Main achievement was to reach ``ASIC-like'' design cycle time (9months for 1.2Mxtors), but keeping full custom performances in terms of density (9 KGates/sqmm2, 0.5 um process).
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Thomson Consumer Electronic Components
- Digital Libraries Group Leader
1991 - 1993
Head of a 4 people team
Responsible of design methodology for digital library development:
- setting up in 4 months of a whole set of 0.7um library used successfully in more than 10 designs, including Standard cell library, memory compilers, data path elements and I/O library using COMPASS DA tool suite.
- Developing the expertise of project dedicated STD cell libraries to optimize circuit
performances and density. As a result TCEC MPEG audio decoder circuit outperformed the competition
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SGS Thomson
- Project Leader
Arcueil
1989 - 1991
Design of IC for telecom application, Introduction of the first library based design methodology for the group. Use of BICMOS process to design a monochip circuit for telephone set application, including the development of a dedicated microprocessor along with its FPGA emulator.
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SGS Thomson
- Design & CAD support
Arcueil
1987 - 1989
In charge of CAD and design support for SGS Thomson analog array family, bipolar technology,
Development and deployment of CAD system for array personalization by customer.
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SGS Thomson
- Project leader
Arcueil
1984 - 1987
Design of programmable integrated circuits (PALs) using bipolar fuse technology, Specification and interface with programming equipment supplier (Data I/O)
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SGS Thomson
- IC Designer
1982 - 1984
Development of second source of AMD2900 microprocessor family. Transfer of 2901C, 2910, 2909, and 2902 to create a complete design kit
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CII Honeywell Bull
- Design Engineer
1981 - 1982
Developing test programs for central processor units of DPS7 mainframes
