Guilhem SIFFERT

En résumé

Entreprises

• Neotion - Senior Digital ASIC Designer

  2008 - maintenant  Pay TV dedicated SOCs (ARM & secure RISC based)
  - Achievements:
  ▪security companion chips: - GS2: (28 nm/5,7 M gates)
  - NCS4: (40 nm/2,9 M gates)
  - GS1: (65 nm/4,3 M gates)
  - LCS1: (65 nm/1,7 M gates)
  - NKE1: (90 nm/1,2 M gates)
  ▪secure DVB SOC: - NP6: (90 nm/4,2 M gates)
  - Participation in definition and specification.
  - VHDL RTL design and IP integration.
  - Collaboration on test and verification:
  ▪Block level test (VHDL)
  ▪Subsystem/Top level test (C/VHDL), simulation, co-simulation and FPGA-based emulation.
  - Block synthesis and equivalence checking.
  - Responsible of:
  ▪Transport Packet Scrambling/Descrambling (DVB cryptography, key table).
  ▪ Security blocks (crypto, clock monitoring, random generation, side channel attack IP integration).
  ▪ Level2 cache memory (AXI, 4 ways, AES based encryption, CRC).
  ▪ Secure subsystem ROM tests (secure configuration, crypto accelerators, TS crypto).
  ▪ Video pixel scaler (NP6 chip).

• Akka Technologies (formerly Coframi) - Senior Digital ASIC Designer, consulting for: Schneider Automation

  2005 - 2008  Ceres: System On Chip (150 nm/4,6 M transistors), integrated IP 80152, (80x86 & Arm9 interface).
  - Responsible of a CPLD architecture integrated within the ASIC:
  ▪definition, hardware design (Verilog).
  ▪Lexer/Compiler tool to configure these CPLD, from ABEL style sources (Lex & Yacc)
  ▪Test and validation of both CPLD hardware and its configuration tool.
  - FPGA Prototyping of the SOC on a Xilinx Virtex 4 + interface validation with a Xilinx Spartan 3e.
  - Fast serial transmission designer follow-up (up to 10Mb/s, coaxial & optical).
  - C test code:
  ▪Co-simulation (80152).
  ▪Code porting & multiprocessor emulation (80152 & 80186).

• Ziilabs (formerly 3Dlabs, Creative Technology) - Digital ASIC Designer

  2000 - 2005  DMS-02 : Mobile Media Processor (2005)
  (130nm), dual core ARM926EJ, fully programmable processing array:
  - Mobile DDR SDRAM Controller (64 bits, 1,6GB/s) design.
  - IO buffers compatibility checking: Load/Voltage/Frequency (Spice).
  - Embedded: Clock Gating, Voltage Management, Hibernation Modes.
  - Concurrent simulation against real time C model: Comportment & performances analysis.
  
   VPUs: Visual Processing Units for high end graphics (2000 to 2005)
  - Achievements:
  ▪P25: Wildcat Realizm 500 (130 nm/150 M transistors)
  ▪P20: Wildcat Realizm 100 200 & 800 (130 nm/150 M transistors)
  ▪P9: Wildcat VP560, VP570 (150 nm/45 M transistors)
  ▪P10: Wildcat VP760, VP770, VP870, VP970, VP880pro, VP990pro (150 nm/76 M transistors)
  - Responsible of:
  ▪Micro-architectures (internal units) / Area estimate.
  ▪VHDL Design & concurrent simulation against C model.
  ▪Unit level synthesis / Automatic flow enhancement.
  ▪Multiple clock domains.
  ▪Subsystem integration and simulation.
  ▪Fullchip debug.

• SILEX INSIGHT (formerly Barco Silex) - ASIC/FPGA Digital Design Engineer

  1999 - 2000  Real Time Digital Video Transmission (for PHILIPS Medical Systems)
   Custom JPEG Decoder (for Barco Graphics)
  - VHDL Design, targeting Xilinx Virtex (using Xilinx Foundation & FPGA Express).
  - Validation: Test benches & Simulation.
  - Bring up and testing with the video sensor.
   High resolution RLE picture transfer SCSI card (for Barco Graphics).
  - C++ firmware for IDT 79R30xx
  - Ultra Wide SCSI 2 (80 MB/s).
   ASIC Retargeting (for Lacie)
  - Back-annotated netlist (sdf) & Verilog netlist manipulation.

Formations

Pas de formation renseignée

Réseau

Pas de contact professionnel