Mes compétences :
C/C++
ASIC
FPGA
VHDL
Verilog
Universal Verification Methodology
Embedded systems
Python
Entreprises
Bull
- ASIC Verification Engineer(PFE)
Les Clayes-sous-Bois 2015 - maintenantDevelop verification environments of Bull-ASICs (application specific integrated circuit) Control/Status Register (CSR) according to the Universal Verification Methodology(UVM).
- Development of UVM testbenchs.
- Vertical and horizontal reuse.
- Elaboration of verification sequences and Checkers.
- Scripting.
- Debugging.
- Automating the generation of the verification environment.
STMicroelectronics
- Verification Engineer at STMicroelectronics (PFE)
2014 - 2014Develop verification environments of digital IPs (Intellectual property) ST/Imaging dedicated to Mobile platforms.
- Development of UVM testbenchs.
- Vertical and horizontal reuse.
- Elaboration of verification sequences and Checkers.
- Elaboration of a functional cover model.
- Debugging.
- Tools : Cadence-Incisive, SystemVerilog, UVM.
Siemens Mobility
- Development of the control system using the new system from Siemens TIA PORTAL V11.