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Noureddine ERREBBANE

FÈS

En résumé

+12 years’ experience
Layout of Analogue circuits for applications Automotives and Power Management and Audio on the processes 130µm SOI, 111nm,110nm, CMOS and BiCMOS : LBC7 [0.35um], C035 [0.13um], C021 [65nm], CSM0.18, TSMC90nm, 56KHV [0.35um], 58KHV [0.13um], CU018 and CS055n using Cadence Design and Audit tools for companies NXP (France/USA), Atmel (France), Lfoundry (France), Texas Instruments(France), Conexant(USA), Atmel(France), On-Semi Technologies (France) and Wolfson Micro-Electronique(Edinburg).

Mes compétences :
Electronique
Electricité
Microsoft Office
UNIX
Microsoft Windows
Microsoft Excel
Linux
CMOS
BiCMOS

Entreprises

  • MU-Electronics - SENIOR ANALOG IC LAYOUT DESIGNER

    2014 - maintenant MU-ELECTRONICS, RABAT (FREESCALE and NXP France Subcontractor)
    Analog and Mixed Signal IC Layout Engineer from August 2014 --> on going
    Project: Automotive IC (4 year 5 months)
     Layout of Analogue circuits for Freescale and NXP (France) Process 130nm
    - Development of Layout of Integrated Circuits for automotive.
     Layout of Analogue circuits for Freescale and NXP (U.S.A) Process 130nm
    - Development of Layout of Integrated Circuits for Power Management.
     Mission : 3 months in Freescale/NXP France 19 November 2014 to 14 February 2015

  • Sais Innovation Technology (SIT) - Layout des circuits intégrés analogiques et mixtes

    2013 - 2014 Sais Innovation Technology (LFondry and ATMEL France Subcontractor)
    Analog and Mixed Signal IC Layout Engineer March 2013 to June 2014
    Project: Power Management & Audio modules 8 months
     Layout of Analogue circuits for LFoundry (France) Process 110nm
    - LDO Regulator 1V8
    - Audio Amplifier: Input/output PGA, Decoder, Comparator, PLL, Micro BIAS
    Project: Audio modules 8 months
     Layout of Analogue circuits for Atmel (France) Process 110nm
    - Input stage, Headphone, Output Mixers, DAC, PGA DIFFAMP ……
    - BandGap, Oscillator, Comparators, Buffer, ADC Stereo1V8

  • Sais Innovation Technology (SIT) - Layout des circuits intégrés analogiques et mixtes

    2010 - 2013 Sais Innovation Technology Company (WOLFSON MICROELECTRONICS Edinburg Subcontractor)
    Analog and Mixed Signal IC Layout Engineer January 2010 to February 2013
    Layout of power Management and audio modules on Processes: CU018, CSM018, CU035, CSM035, 65nm and CS055n for following projects:
    Project: Power Management and Audio ICs (3years 2months)
     Modules: Analogue Micro Interface, Output Mixers, Left and Right DAC, Output Stage of Class-AB Amplifier…
     Modules: Output Stage Top, Bandgap Reference, Thermal and Short circuit protection…
     LDMOS Power devices layout (DRC, LVS, EXTRACT, ESD)
     Modules: VIDEO BUFFER…
     Modules: Charge pump, Automatic Gain Control…
     Modules: LDO Regulator, Comparators…
     Modules: Output Stage Module Top and Sub blocks,
     Modules: Output Programmable Gain Amplifier Top
     Modules: LDO regulators 50mA, 150mA
     Modules: LDO Regulators
     Modules: Logic Cells, Analogue Inputs, Micro Bias, Output PGA, Automatic Gain Control Top, ADC Left, ADC Right, Speaker Output Top, Class D/AB Audio Amplifier
     Modules: DAC Top, Bias Generator, PLL, Programmable Gain Amplifier
     Modules: Speaker Driver TOP CSM 0.18um LDMOS

  • DESIGN AND DEVELLOPEMNET CENTER (CDD) - Layout des circuits intégrés analogiques et mixtes

    2009 - 2009 CDD Company (TEXAS INSTRUMENTS France Subcontractor)
    Analog and Mixed Signal IC Layout Engineer April 2007 to Mars 2009
    Project: OMAP Processor companion Power Management & Audio IC (2year)
     Layout of Battery Charger Interface modules: Techno 0.13um
    - LDO voltage Regulators: Sim card, Digital Baseband, Real Time Clock…
    - Comparators, Level Shifters, Digital cells, Thermal Shutdown
     Layout of Audio modules: Techno 0.13um
    - Integrator, Diff Amplifier, Level Shifters, Analog Bias
     Layout of LDO regulators: Techno 0.13um

  • DESIGN AND DEVELLOPEMNET CENTER (CDD) - Layout des circuits intégrés analogiques et mixtes

    2006 - 2007 CDD Company (CONEXANT USA Subcontractor)
    Analog IC Layout Engineer December 2006 to Mars 2007
    Project: Audio Amplifier 4 Months
     Layout of class D Audio Amplifier : Techno: 90nm
    - Modules: Integrator, Clock Detect, Oscillator, DAC Left, comparators…

Formations

  • DESIGN AND DEVELLOPEMNET CENTER (Fès)

    Fès 2006 - 2006 internship IC Layout & Design (6months)

    internship IC Layout & Design (6months)

  • FACULTE OF SCIENCE USMBA UNIVERSITY FES (Fès)

    Fès 2001 - 2006 Master Engineering in Electronics

    BAC+4

  • Lycée Technique (Fès)

    Fès 1998 - 2001 Baccalauréat technique série Electrotechnique

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