Perrin NJOYAH NTAFAM

En résumé

Entreprises

• STMicroelectronics - Ph.D CAD (Computer-Aided Design) Development Student

  2014 - maintenant My research principally focus on pré-silicon software performance estimation and optimization using cycle accurate virtual models available within an ISS (Instructions Set Simulator). We exploit observability provided by such models to explore and characterize the way the executed benchmark upon the virtual platform is actually exploiting future SoC capabilities. We identify bottlenecks, then we experiment and develop a reliable methodology which allows estimating and improving non-intuitively the way the benchmark uses the hardware.

• STMicroelectronics - CAD Development Engineer (End of Engineering degree internship )

  2014 - 2014 ☛Build of a virtual platform (VP) designed around the Cortex A9 processor within SoC Designer tool which is an ISS (Instruction Set Simulator). Using example of source codes provided by tool support ( SoC Designer), we wrote C and ARM assembly codes to initialize the platform ( L1 & L2 caches, global data, entry point, L2 cache latency and configuration, ...).
  ☛Estimation using cycle accurate virtual models of Dhrystone benchmark performance by extracting architecture information during the benchmark execution within SoC Designer ISS. Architecture information are obtained from PMU (Performance Monitoring Unit) registers, which helped characterizing L1 and L2 cache memories usage.
  ☛Assessment of CPU frequencies and L1&2 cache memories influence on system and software performance by comparing execution time in terms of number of execution cycles of Dhrystone and Whetstone benchmarks.
  ☛As SoC Designer tool allows generating fast models (FM) of the processor to run the target application in instruction accurate (IA) mode and then swap to cycle accurate (CA) mode, I built a platform representing the needed subset of a typical ST’s platform, to boot in IA mode, a Linaro embedded Linux OS that we first compiled, and then we swapped to CA mode to run a specific application on top of the Linux Kernel, a simple Dhrystone benchmark in my case (goal being platform flow demonstrator rather than benchmark, for now).
  ☛Start built of a mixed virtual platform containing CA models and ST components implemented in TLM.
  ☛Keywords : CortexA9 architecture, Cycle-accurate & Instruction-accurate VP, Benchmarking, Cache characterization, Cross-compiling, Linux kernel generation, Software-on-VP estimation, , SystemC, SoC Design flow,

Formations

• Institut National Polytechnique De Grenoble (INPG)

  Grenoble 2014 - maintenant Doctor of Philosophy
  
  Ph.D studies in collaboration with STMicroelectronics in order to acquire both industrial and academic skills.

• Universität Paderborn (Allemagne)

  Paderborn 2013 - 2014 Msc. Computer Engineering
  
  Evolutionary Robotic, Swarm Intelligence, Mobile Communication, Real Time OS, FPGA System, Advanced Computer Architecture, Cache Characterization, SPARC Architecture, LEON 3.

• Ecole Nationale Superieure Des Ingenieurs Du Mans (ENSIM)

  Le Mans 2011 - 2013 Ingénieur Informatique
  
  Embedded Development (C/C++), Drivers Coding, Microcontrollers Programming, Digital Electronic, Real Time Operating Systems, ARMv7 Processor (CA9 ISA + ASM), Embedded Linux Re-compilation, Signal and Image Processing (Matlab, Simulink), Test & Quality, Performance Estimation and Optimization, Project Management, Cost Management, Market share study...

Réseau

• Arnaud Cedric KENGNE KUITCHE

• Justin BACLE

• Labiba VINSON

• Philippe ANGEL

• Solène BALOGOG

• Sylvia LIARD-PERRARD

• Thomas ROLAND

• Victor KUATE