Abdel ETTAYACH

En résumé

Entreprises

• ST Microelectronics - Design For Test Engineer (EASII-IC consulting)

  2011 - maintenant Design for test activities on multiple wireless ASIC projects
  
  • In charge of MBIST, DPHY and Efuse verification (RTL, Gate Level zero delay and SDF) based
  on 1500 programming in Top-level and subs-system.
  • DFT scan insertion with compression and 1500 wrapper (used specific STM flow and DC)
  • ATPG Flow steup with scripting TCL
  • ATPG patterns generation and simulation (MAXTB and STILDPV): Stuck-At fault, Transition Faults (Gate Level zero delay and SDF)
  • Following-up and reporting results for optimization
  • Work closely with designers, architect, Middle End and Back End team, Product Engineer, client support team
  

• Alcatel Lucent - ASIC Design Engineer (ELSYS DESIGN consulting)

  Paris 2010 - 2010 Design and verification on embedded ASIC used for UMTS/WCDMA network
  
  • Upgrading specifications on relevant modules to implement the new constraints of 3GPP
  • Updating VHDL design on each TX transmission modules
  • Verification with C model as a reference
  

• Elsys Design - Solution Design Engineer

  Cachan 2009 - 2009 Feasibility study for microprocessor 68xxx’s treatment of obsolescence
  
  • Investigation into the needed elements for microprocessor development
  • Research for the compiler, debugger, simulator
  • Study of microprocessor 68xxx documentation, Analysis of 68xxx development’s existing solutions
  • Definition of the conception strategy, Architecture of characterization and verification board
  

• Elsys Design - Embedded FPGA design Engineer

  Cachan 2009 - 2009 Design, verification and synthesis on embedded FPGA
  
  • Design of module which controls the generation of radar impulse integrated in the top level
  • Test development , simulation environment and RTL verification
  • Verification with C model as a reference
  • FPGA synthesis Timing constraints definition and critical path analysis
  • Post-rout optimization
  

• Thales - Digital verification Engineer

  Courbevoie 2008 - 2009 Stress test bench development for FPGA integrated into the A320 avionics calculator
  
  • Study of FPGA specifications and its interfaces EBI, PUMA and RAM
  • Development of PUMA, EBI emulators and RAM to generate random access
  • Development of top level test bench integrating FPGA and emulators
  • RTL simulation and verification
  • Adding timing constraints to the emulators to simulate post-route, Post-Route simulation and verification
  

• Texas Instruments - Digital Engineer

  Villeneuve-Loubet 2006 - 2008 Functional DFT verification in System-DFT group of the Wireless
  
  • Leading and Managing tests of analog/power modules (HDMI, CSI, DSI)
  • Test development using JTAG access and simulation RTL and Gate for BIST modules (RNG, DLL, LDO)
  • ATPG patterns generation: Stuck-At, Bridging Fault and Path delay
  • Work closely with designers, architect, product engineer, client support team, on site and abroad
  

• Thomson Video Networks - Processor Design Engineer

  Ille-et-Vilaine 2006 - 2006 Processor design and integration used for ASIC/FPGA applications
  
  • Design of microprocessor (RISC) modules intended for a chip control application used
  for the camera video treatment.
  • Verilog design of existing blocks to make them synthesizable
  • Testbench development, RTL simulation and validation, FPGA synthesis optimization
  

• Thomson Video Networks - Hardware Emulation Engineer

  Ille-et-Vilaine 2005 - 2006 Hardware emulation on Digital decoder used for set top box
  
  • Synthesizable test bench development for emulation: Integration of blocks needed to validate
  the video decoder (ARM memory controller, DDR, APB/AHB bridge …)
  • Functional validation by RTL simulation of video decoder sub-system
  • Script development for emulation environment: netlist, compilation and debug file generation
  • Emulation of video decoder sub-system and gate validation
  • Integration, emulation and verification of the video decoding block in the top level environment
  

Formations

• IAE Grenoble

  Grenoble 2011 - 2013 Master Business Administration

• INPG

  Grenoble 2003 - 2004 Master Integrated Digital and Analog Systems Design

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