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Alexandre APCHER

TOULOUSE

En résumé

A highly resourceful, flexible, innovative, and enthusiastic project manager.
Possessing considerable experience of managing projects from beginning to end,
defining the project plan, timeline, scope and executing the analysis before providing
detailed recommendations. Having skills of delivering major operational
improvement and of orchestrating people, schedules and resources for optimum
productivity, efficiency and quality. Keen to find a challenging position within an
ambitious company where I will be able to continue to increase my project
management skills.

Mes compétences :
Integrated Circuit
Analogue Circuits
project management
manage an experimented IC
TQM
Responsible for the Physical design
Responsible for physical design implementation
Physical design
DFMEA
Cadence Software

Entreprises

  • On semi - Manager

    2008 - maintenant

  • ON Semiconductor - Project manager & physical designer

    TOULOUSE 2008 - maintenant & r physical designer leader - ON Semiconductor,
    Responsible for estimating the work to be done, identify dependencies, critical path
    activities, & the resources needed for each project. Also in charge of leading various Integrated
    Circuits enabled initiatives in a fast paced team and in a changing organization/projects.
    Manage projects, and drive the project team from start through to completion.
    Define project scope, objectives, milestones and deliverables.
    Pro-actively manage project risks and issues and minimize their impact on the project.
    Regularly communicate project expectations to team members and stakeholders and use
    their feedback to optimize progress.
    Negotiate use of resources in a matrix management environment.
    Coordinate and manage project reporting, project reviews and project steering meetings.
    Responsible for the Health, Safety and Welfare of all team members.

    Layout leader of full custom layout of high power analog circuits and chips with Cadence VXL
    on a very aggressive schedule. Lead the layout top cell and effort on the chip that was awarded EDN's
    Hot 100 Products for 2012 in the `Power' category.
    Responsible for the Physical design of Analog Circuits in a fast paced environment and carry
    to completion block level and project lead level developments complying with specifications.
    Active role in initial schedule creation, providing accurate estimates that ensure meeting
    deadlines and speed up the completion of the block or project and guarantee the certainty of a
    delivery on time or before the deadline.
    Close collaboration with the design team, group leaders and management.

  • ON Semiconductor - Manager

    TOULOUSE 2008 - maintenant Management of layout team: plan, organize, coordinate and optimize layout team workload,
    coordinated resources to provide highly competitive solution due to the project requirements, to
    maximize design/methodology reusability among projects and to insure on time the solution
    deliveries. In 7 years the team has grown from 4 to 7 engineers, hiring 4 new layout team members
    with success and very good integration in the team and on projects.
    Manager responsible for career development of direct reports as well as maintaining a role
    as individual contributor to physical design teams. Facilitation and implementation of miscellaneous
    process improvement tasks aiding in productivity, quality enhancement and path finding are
    additional responsibilities.
    Owner of physical design methodologies and flow automation, continually seeking to
    improve process and procedures, responsible for one of the most productivity booster scripts that
    enable the team to run automated verification checks.

  • Freescale - Physical design engineer

    Toulouse 2007 - 2007 Physical design engineer for automotive product. (Short experience 4months)

  • STMicroelectronics - Physical design leader & contractor

    2003 - 2007 Responsible for physical design implementation of complex Test chip in which challenges
    such as high performance, power management, low power and high speed design where addressed.
    Ownership of tasks such as main macro integration and floorplan, top level bump map design
    and floorplan, top level verifications, high speed and critical analog layout, schedule tracking and
    project management support.

    Working on latest experimental technologies. Owned full chip designs as layout lead on
    multiple projects
    Among other responsibilities, Project Management and scheduling support, Task Tracking
    progress and Document control.

  • STMicroelectronics - Contractor

    2001 - 2003 Physical design junior - contractor @ STM, Crolles, Layout Engineer
    Project Management for development devices test procedures on advanced technologies
    Designer of process control monitoring structures for advanced technologies 500 nm and 65
    nm ,

  • MICHELIN - Electro-technician

    FERRAND 1998 - 1999 Sandwich Formation 1 month in the university and 1month in Michelin
    Training based primarily on total quality management: how define a specification? how to
    check the feasibility of projects? How measure the risks with the DFMEA (AMDEC)? How and when
    take the preventive actions?
    Project in Michelin: pass a prototype machine to production machine

Formations

Pas de formation renseignée

Réseau

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