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Alexandre BETAT

Stockholm, Sweden

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Aix-en-Provence ainsi que le résultat des européennes dans les Bouches-du-Rhône.

En résumé

IC Layout Design
Technical leadership, resource & task management of physical design.

- Full-custom layout analog, RF, NVM & IP blocks.
- 28 nm, 22nm SOI, 16 nm finFET.
- High frequency (up to 40Ghz)
- Deliver a chip design from scratch layout to tape out.
- Chip floor planning lead / Top level chip assembly.
- Mix chip integration and IP placement constraints.
- Signal integrity at chip level layout placement.
- Pad ring layout / Power routing.
- Block sizing and pin assignment.
- Analog blocks constraints (device matching, signal sizing, guard ring ...).
- Mixed signal blocks constraints (limit cross talk, signal integrity ...).
- Layout verification (DRC, LVS, DFM).
- IP layout, integration and management
- Digital blocks place and route.
- Revision control and database management. (DesignSync).
- Interface with silicon foundry for tape out.
- Coordinate various activities with process, lithography, packaging, design and CAD groups.

- Tasks, Timing and resources budgeting / management.
- Layout tasks scheduling.
- Layout flow leader.
- Co-ordinate external technical people involved in the project.
- Design-to-fab interface for Tape-out.
- Employee training and improvement.

Specialties:
Computer languages: Skill, Sed, Awk, Shell, Verilog.
Tools : Smash, Eldo, Analog Arist (simulation), ICCraftman, Silicon Ensemble, First Encounter (Place & route), Slam, Virtuoso, VirtuosoXL (Layout), Diva, Calibre, PVS, Assura, Hercule (verification DRC/LVS), Mask Compose, Place (reticle)

Mes compétences :
Microélectronique
Tape Out
Coordinating tasks
Layout analog
Calibre
LVS
DRC
Physical design
Mask Design
Floorplanning
Assura
Scheduling

Entreprises

  • Huawei - Freelance RF IC layout

    Stockholm, Sweden 2016 - maintenant - Full-custom layout analog, RF, IP blocks.
    - 28 nm, 22nm SOI, 16 nm finFET.
    - High frequency (up to 40Ghz)

  • INVIA - IC Layout Design Manager

    2015 - 2016

  • INVIA - Senior Analog/RF/NVM IC Layout Designer

    2014 - 2016

  • NXP Semiconductors - Freelance Tape Out Engineer

    Nijmegen, Netherlands 2013 - 2014 Senior Tape Out Engineer / Mask Layout Designer / Reticle Design Engineer

    - Checking quality of incoming chip design layouts (design rule checks, manufacturability
    checks, ...)
    - Translate electrical chip designs into manufacturing designs and orders resulting master
    plates (reticles or photo masks).
    - Filling fab/foundry systems with the appropriate data required to run the correct wafers with the right photo masks.
    - Handle tape outs of product layouts provided by design teams.
    - Chip finishing, verifying product layout and photo mask data, ordering photo masks, introducing the product in the fab and managing MPWs.
    - Building SPW/MPW reticles.

  • Inside Secure - Senior Analog IC Layout & Back End Team Leader

    Meyreuil 2008 - 2012 Senior Analog IC Layout & Back-End Team Leader

  • Inside Secure - Senior Analog IC Layout

    Meyreuil 2004 - 2008 Senior Analog IC Layout

    Layout implementation of different analog blocks and mixed signal IP's.

    IPs realisation :
    - Memories : EEPROM, RAM and ROM.
    - Analog blocks as BandGap, RF, PLL, Pad Esd, Clock Extractor ...

    Chips realisation :
    - Floor planning, place and route of smart Card, NFC, RFID product.

  • Amesys (Artware) - Layout consultant

    2003 - 2004 One year consulting at Atmel (Rousset) :
    - Layout full custom of power management blocks.

    Six month consulting At RFMagic (Sophia Antipolis) :
    - Layout full custom of RF IP blocks.

  • Dolphin Integration - Technicien Topologue

    Meylan 1999 - 2003 Layout custom of memories blocks

    - Bit-cell SRAM and ROM density optimization.
    - Layout implementation of several memories compilers SRAM, ROM and DpRAM in 0.25µm and 0.18µm.
    - Layout from scratch of the whole memories compiler.
    - Specifications of the reuse of internal memories blocks to be integrated and fit with all the memories sizes.

    - Management and trainings of layout project team.
    - Scheduling.

Formations

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