Villeneuve-Loubet2000 - maintenantWireless Terminal Business Unit: Integrated circuits design engineer on mobile phones digital devices using very deep sub-micron technology.
2008-2009: Theoretical analog training delivered by an analog expert senior designer teacher(1h30 per week)
2008-2009: Modem for lead customer: Top level BE designer and BE activity coordinator
In an off site lead customer project team, I was in charge of:
• Top level floorplan design according to blocks constraints due to analog/digital subchips
• I/O definition and placement to fit customer chip's package constraints
• Chip placement and routing using several parallel databases
• Clock routing and post clock tree optimization on several parallel databases
• Static and dynamic power consumption analysis and IRdrop improvement by floorplan
update and/or placement and/or routing (layer changes)
• Customer CAD environment training, setup and follow-up
• Front end customer support on all technical issues faced during the project back end
phase (TI flow, tools, floorplan proposals, routing optimizations...)
• Project back end environment setup, follow-up using database management tool and
support
• Customer and TI back end teams tasks definition and schedule
• Conference calls setup and lead with program manager: involving customer and the
different development teams including TI and off site subcontractors
2006-2007: Modem for lead customer: Top level Back End designer
In a multi-site lead customer project team, I was in charge of:
• TI back end flow quality improvement with a new power tool evaluation and validation
using existing chips as test chips, to fit lead customer needs
• TI back end flow customization to integrate this tool. Results of my study have been
applied to the very next flow version by the TI CAD team (US and India)
In parallel of this previous role, I was also in charge of:
• Project's back end schedule and tasks definition up to PG on both customer and TI teams
• Conference calls setup and lead with customer as front end support on all technical
issues faced during the project back end phase, also tracking them up to resolution and
continuously keep project on track with schedule
2000-2005: DSP for mobile IC: Subchip Back End designer
After 1 month back end formation, I was in charge of:
• memory subchips floorplan, placement and routing
• CPU subchips placement, routing and routing optimization
• Static power consumption analysis and improvement by floorplan changes
Mentor Graphics IP Division Sophia Antipolis (06)
- IC Front End Design engineer
1998 - 2000PowerPC4Ol : Hard macro and Test chip design in UMC O.l8micron
• Verilog RTL code checking (Lint, portability to VHDL, testability, RMM compliance)
• RTL and Gate level simulation (compliance tests)
• Synthesis and static timing analysis
• Formal verification RTL and Gate level
Translation VHDL to Verilog and Verilog to VHDL
• Flow definition, implementation and validation for Reusability.
• 9 cores translated from 5k gates to 15k gates
• Lint, code coverage, RMM compliance and design portability
• checking, simulation, synthesis, formal verification RTL and Gate level
CER IBM la Gaude (06)
- Design
1989 - 1998Jan 97 - Jan 98 CER IBM la Gaude (06)
• Design of ATM switch in VHDL
• Simulation and Synthesis
• FPGA prototyping
June 92 - June 93 CER IBM la Gaude (06)
• Design of ALU and Extended ALU of processor for ASIC implementation of
telecommunication network management hub
• Validation by VHDL simulation, synthesis and FPGA prototyping
Jan 92 - May 92
• Training in Telecommunication networking, with software implementation of
“Minitel” server and Transpac Modem, used for online shopping
Jul 89 - Mars 91 CER IBM la Gaude (06)
• Following my training period, Design of control unit (CCU) of RISC processor for
Telecommunication application. (simulation, synthesis, static timing analysis)
