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Benoît SUFFRAN

LE SAPPEY EN CHARTREUSE

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes au Sappey-en-Chartreuse ainsi que le résultat des européennes dans l'Isère.

En résumé

Experienced Design and Validation Engineer with a demonstrated history of working in the semiconductors industry.
He is comfortable with a variety of languages (including Verilog, VHDL,C/C++, TCL and Python) and design tools (such as Vivado, ISE, and Quartus).
Education featuring hardware design and prior work in software development allows him to be a valuable contributor in a wide range of group discussions.
Autonomous team member with first class interpersonal skills and thirst of learning, who make things progressing rapidely and safely.

Entreprises

  • ST Microélectronics - FPGA product owner for NFC products, Member of technical staff for FPGA competencies

    2016 - maintenant ASIC to FPGA prototyping activity to NFC market.
    • Deliver a validation platform pre tapeout.
    • Ensure full functional compatibility of FPGA platform compared to RTL design: be able to write corresponding modifications specific to FPGA and validate them exhaustively.
    • Ensure/implement debug capabilities to ease validation done by internal customers: Product owners and test engineers

  • STMicroelectronics - Security Validation Engineer

    2015 - 2015 Owner of test application for Nagra’s IP in STMicroelectronics’s chip.
    • Understand a complex system with Hardware, Firmware and Driver
    • Pre-silicon validation on Mentor Graphics Veloce platform.
    • Test plan and Silicon validation.

  • STMicroelectronics - FPGA Staff Engineer for Set Top Box product

    2012 - 2015 ASIC to FPGA Prototyping activity to Set-top Box market.
    • Technical project definition, specification.
    • Implement test and document technical solution.
    • Co-Prototyping IP like USB3, HDMI2.
    • Design of AXI3, 4, ACE, ACE-Lite transactor.

    • Writing paper:
    SUFFRAN B. (2013) Prototyping a Large Multi-CPU SoC onto Multi-FPGA Boards using Certify Pin Multiplexing Techniques A5, review SNUG
    SOL L., SUFFRAN B. (2012) Synopsys Cookbook to Reduce Congestion on Virtex6 Designs B5, review SNUG

  • ST Ericsson - Prototyping Engineer FPGA

    GRENOBLE 2007 - 2012 FPGA prototyping of several mobile phone platform.

    • Prototyping ARM core (cortex A9, A15, A7, M4)
    • Partitioning, synthesize RTL.
    • Co-Prototyping Platform Design RTL+BFM+Software SystemC.
    • Board Specification to Pre-silicon activity.
    • Flow automation (perl, tcl).
    • Technical support of team based abroad.

  • Temento Systems - Ingénieur RTL

    2004 - 2007 Software design of a debug tool to FPGA using JTAG interface.

    • Software development of low level API in C++.
    • RTL design of IP to debug FPGA.

  • CNES - Toulouse - Enginneer

    PARIS 1 2003 - 2003

Formations

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