2009 - 2010Développement et vérification des couches basses logicielles pour des plateformes de téléphonie mobile 3G/4G.
ST Microelectronics
- Expert Verification (Specman)
2008 - 2009Vérification top level d'une plateforme de téléphonie mobile LTE. Mise un place d'un nouveau processus de vérification d'intégration des sous-modules autour de l'interconnect AXI/STBUS.
SDV CONSEIL
- Gérant
2007 - 2010Fournir des prestations de conception, vérification en micro-électroniques au entreprises du secteur (Texas Instruments, ST Microelectronics, ST Ericsson, FreeScale ...)
ST Microelectronics
- Expert Vérification (Specman)
2007 - 2008Je suis responsable de la vérification fonctionnelle et formelle d'un module d'interfaçage entre un ou plusieurs écrans et la puce multimédia pour des téléphones mobiles de 3ème génération.
Au sein d'une équipe multi-site et multilingues (3 continents) de 5 ingénieurs en vérification, je suis l'expert de la méthologie et du langage E de l'outil Specman (Cadence) ainsi que des techniques de "property checking" sous Rulebase (IBM).
Villeneuve-Loubet2005 - 2006Verification of mixed signal power management chip family (3 products) for 3G/3.5G phone platforms using Specman/Modelsim/Nanosim/Cadence
1st Phase : Power subchip verification
- Define/Design verification environment (eVC methodology)
- Define new verification flow for mixed signal simulations
- Define testplan and write test cases
- Run test cases, code coverage (VNavigator) for RTL simulations
- Train and manage 1 analog designer (on-site) on Nanosim simulations and netlist analysis
2nd Phase : Power subchip verification leader on 3 products
- Define verification environment (eVC methodology) and testplan
- Create critical test cases (random generation)
- Train and manage 2 verification engineers (India) to write the environment and the test cases, run simulations and code coverage
- Train and manage 2 analog designers (on-site and Morocco) on Nanosim simulations and netlist analysis
- Report status of the 3 chips to the management on a weekly basis
- Define design enhancement according to 1-year experience on 3 different power management chips for both digital and analog
3rd Phase : Chip verification leader
- Lead the verification of the last power management chip generation
- Define verification project plan
- Track status of the 5 subchips leaders (USB/AUDIO/POWER/BatteryIF/TOP). The whole team is 30 engineers on 3 continents.
- Define architecture/design enhancements
2003 - 2005Structural and functional verification of several communication chips (4 to 8 millions gates) for metropolitan networks (Ethernet over Sonet) using Specman/Modelsim.
- Define/Design verification environment
- Define code coverage and functional coverage metrics.
- Define testplan
- Run testcases and code coverage
Introduce assertion based verification to the company (PSL with Magellan and SafeLogic)
2002 - 2003Protocol stack design and verification in C for a DSLAM network processor
- Functional specification writing (ATM, PPP, IP, MPLS, Ethernet)
- Validation plan writing
- Application and testbench coding in C
- Integration on a Tensilica processor
Market study on WLAN chips opportunity for TranSwitch (WiFi)
