2011 - 2012Interface IPs development group, within the Digital SOC division.
IP developments supervision (functional role).
Design flow and development process improvement for IPs and subsystems.
Fpga prototyping activity creation and ramp-up (focusing on IP validation and IOT).
Location: Rabat, Morocco.
ST-Ericsson
- IP Design Manager
2008 - 2011Line manager of a digital IPs design group: Design, Verification, EDA – 52 people overall.
Management of three lines involved in IP development activities: RTL design, functional verification, EDA support.
IP portfolio composed of serial interfaces, memory interfaces, cryptographic accelerators, Trace & Debug and fabric elements (55 IPs in total).
Design flow and development process improvement.
Proactive interaction with the local ecosystem, reinforcing links with Universities and local companies.
Location: Rabat, Morocco.
STMicroelectronics
- SOC integration leader
2005 - 2007SOC integration leader. 3G/HSPA baseband devices with advanced multimedia features (38 million units produced).
Functional manager (object leader) for a 10 people RTL integration team.
Responsible for SOC RTL releases’ execution, with strong focus on predictability and quality of the deliveries. Functional and implementation issues to be tackled as much as possible at this level.
Interfacing with the two SOC Project Leaders based in Grenoble and Lund-Sweden, as well as Architecture, Verification, RTL2gate and DFT object leaders.
Work load allocation, and accurate developments planning & tracking.
STMicroelectronics
- Frontend Design Engineer
2005 - 2005SOC integration at our customer (Ericsson Mobile Platforms - EMP).
Location: Lund, Sweden.
Formations
INPG - ENSERG ENSERG (Grenoble)
Grenoble1995 - 1998Diplome d'Ingenieur en Microelectronique
