Mes compétences :
Advanced
Coordination
Foundry
manufacturing
PDCA
Qualification
reliability
Test
Entreprises
Presto Engineering Europe
Caenmaintenant
NXP Semiconductors
- Senior Troubleshooting & Problem Solving team Leader
Colombelles2005 - maintenantApril 2005 – Present (2 years 1 month)
Missions:
1- Garantee the introduction of new products:
1.1- Manage new product introduction and problem solving projects.
1.2- Coordinate sustainabillity of the ramp activities (crisis situation management)
1.3- Improve processes for NPI
2- Interface to the Product Development, and all Operations teams:
2.1- Represent Operations within project core teams.
2.2- Use in-depth knowledge of production processes to influence design focused on manufacturability, testability, flexibility, cost, etc.
2.3- Understand key cost drivers and influence Engineering, and Operations, teams to realize cost reduction opportunities and eliminate risk.
3- Responsible for the operational metrics, which include First Time Right, cost, quality:
3.1- Escalate key product issues to Operations executive team through weekly reviews. Synthesize a multitude of issues to achieve a clear, focused message.
3.2- Implement business cases to contain problems and get corrective actions.
Concrete successes in the field:
- Improved by 7% the CMOS90 lead edge bluetooth chip overall yield, ~ 6.5 M€ cost recovering
- Solved speed limitation of the CMOS90 multimedia processor (TriMedia core), deployed on other cores
- Increased by 4% CMOS120 printer chip yield to support the end customer cost shrink, ~ 2.3 M€ saved
- Managed the emergency response to secure CMOS90 mobile multimedia chip supply chain in TSMC
ARM
- R&D Library Project Leader
2001 - 2005August 2001 – February 2005 (3 years 7 months)
Since 2001-2005:
SOISIC has been founded by renowned SOI experts as a spin-off company from CEA (LETI and DAM), the world class french research organization. SOISIC expertise covers fully-depleted and partially-depleted SOI CMOS technologies and circuit design. SOISIC is now part of the ARM compagny as physical IP design department.
I worked from the startup time to the rampup activity as memory compiler architect (SRAM/DSRAM/ROM) in advanced SOI process nodes. I was responsible for the specification of the IP and the project leader of the development phase. In charge of R&D program that my activity led to 2 worldwide patents to structure and protect the compagny IP portfolio. I also collaborated to the standard cell library development by an active role in work flow setup and implementation.
Key roles/Responsibilities:
- Compiler architecture definition up to datasheet specification with end customer
- Foundries’ memory bitcell electrical characterization and validation
- Design phase scheduling and execution management from schematic to post layout simulation
- Software code specification and software external provider interface management
Concrete successes in the field:
- Double the patent licensing count to protect the start-up know-how
- Manage participation in R&D European Program (MEDEA+ T206) to fund the company R&D efforts
I left the compagny on claims of PHILIPS to take over the debug activity in the industrialization department in Crolles2 (PHILIPS Semiconductors became NXP Semiconductors end of 2006).
STMicroelectronics
- R&D Desgin Enigneer
2001 - 2001February 2001 – October 2001 ( 9 months)
In the framework of my final internship, I have been responsible for the retargetting of an existing embedded SRAM compiler towards a very specific architecture to be compatible with a Quasi Delay Insensitive asynchronous protocol. It has been used to generate the macros needed for an asynchronous microprocessor in CMOS 0.18 um. I collaborate closely within the Central R&D Dept with the memory development group to make sure such modification are sustainable in terms of design automation constraints.
In parallel, I worked on a very specific feasability study to create a single event upset (SEU/soft errors) robust memory archiecture. It led to interesting patent opportunities.
THOMSON PLASMA is a former subsidiary of THOMSON Multimedia focused on Plasma flat planel for TV screen application. As final internship in the framework of my graduate, I took over the study of plasma coplanar pixel espacially to improve light efficiency (yield between input energy and light emitted). I developed analytical model to explain the fluctuation of this yield with respect to all the structural parameters of the pixel (electrode geometry, dielectric material, ...). My work led to a compagny patent end of 2000.
