-
RivieraWaves
- Senior digital design engineer
Biot - Sophia Antipolis
2010 - maintenant
Bluetooth Low Energy IP implementation in Verilog with System Verilog assertions, verification;
-
Wipro - Newlogic
- Senior digital design engineer
2007 - 2010
- System definition on 802.11n MAC HW IP, implementation of receive path and timing reference block in Verilog and System Verilog assertions, verification team support;
- 802.11abg SoC for video games application with ultra low power performances: responsible of chip and platform integration, radio controller and CCA blocks implementation, power management implementation, RF modeling, top testbench implementation, FPGA prototyping on Xilinx Virtex 4, verification and back-end teams support.
-
Wipro - Newlogic
- Digital Design Engineer
2002 - 2007
- 802.11bg SoC for sensors application with dual ARM processor platforms: responsible of chip and platform integration, peripheral IP implementation, top testbench and verification, front-end and back-end teams support, silicon validation and SW team support;
- design service on multi-core ARM based 3G platform: system definition on MMC and DDR IP selection, FPGA prototyping and partitioning on Xilinx Virtex 4, FPGA testbench implementation, customer training;
- 802.11 abg chip testbench implementation in VHDL and verification (RTL and gate level);
- OFDM modem blocks and top level verification and optimization, prototyping on FPGA Xilinx Virtex 2;
- DSP front-end blocks implementation in VHDL for OFDM modem;
- Bluetooth chip verification and debug investigation on small peripheral IP blocks, BIST RAM and ROM implementation in VHDL.
