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Fabien SENILHES

GRENOBLE

En résumé

Date of Birth:12/04/1977 Nationality:French


EDUCATION:
2001 - 2002
Establishment: University of Clermont-Ferrand (63), France
Degree obtained: Master of Analog Microelectronic.
Area of major concentration: Design of analog integrated circuits.

LANGUAGES:
French (mother tongue)
English (spoken and written)
German (notions)

TECHNICAL SKILLS:
• Expert user of Cadence Mixed design framework (Composer, Analog Artist, Hierarchy Editor.)
• The good knowledge of HDL languages (VHDLAMS, VHDL, Verilog / VerilogA / VerilogAMS).
• Expert user of Mentor Graphics AMS product line (Eldo, EldoRF / Modelsim / ADVance Ms, ADVance MS RF / Adit, Mach, EZwave).
• Experience with others analog / digital / fast simulators (MICA / VERILOG / Nanosim).
• Experience with calibre to extract the parasitics in order to perform back-annotated simulations.
• Experience with synthesis tool (Design Compiler, Design Analyzer)
• Experience with Virtuoso layout editor and the Silicon Ensemble tool.
• The understanding data management concepts and the ability to work with a revision control system with teams accessing a common repository from multiples sites. (Synchronicity)
• Experience with the Mentor Graphics design framework (Design Architect) and the Mentor Graphics PCB tools (PADSPowerlogic / PADSPowerPCB).

Mes compétences :
CAD
Cadence
Design
EDA
Graphics Design
MENTOR
Mentor Graphics
SYnopsys

Entreprises

  • Motorola Semiconductors, Toulouse (France) - Analog Designer Trainee

    maintenant Position: Analog Designer Trainee as part of Masters degree within WBSG / EMEA power management division.

    Mixed Circuit Design Experience:
    • Investigate on the feasibility of DC-DC voltage converter (stepdown) including digital control. Use behavioral models to validate the system (VerilogA / Verilog language).
    • Re-design analog cells (ldo, comparator, power driver).
    • Design the digital control part (front end and back end).
    • Evaluate the performances of first silicon in the lab.
    Additional Mixed Design Skills / Responsibilities:
    • Good knowledge of ASIC design flow.

  • Mentor Graphics, Grenoble (France) - CAD/EDA Engineer: Analog Mixed Signal

    2003 - maintenant Position: CAD/EDA Engineer – AMS (Analog Mixed Signal) Modeling and Simulation within Wireless Communication Division of STMicroelectronics.
    Job Description: To develop VHDLAMS models for analog / mixed signal / RF ICs and perform top level simulations in collaboration with design leader and customers. To provide tool support.

    AMS Modeling / Simulation / Support Experience:
    • Develop many specific VHDLAMS models (Pll, Vco, Adc, Dac, Audio Converter, Oscillator, DC-DC, Ldos, Comparator, Reference voltage / current …) for several power management and RF applications. Characterize the behavioral model in simulating the IP in transistor level.
    • Create generic VHDLAMS models for ST internal library.
    • Define the verification strategies with leader project and perform the functional top level simulations.
    • Participate in the development of RF / mixed signal simulation methodologies in order to improve the efficiency of verification flow.
    • Collaborate with design teams to provide tool support, trainings and presentations (mixed signal top level simulation, VHDLAMS language, new tool functionalities, viewer …)
    • Diagnose and decompose Mentor graphics AMS software-related problems. Assign the defects to Mentor Graphics engineering and define the functional specification of new requirements or new tools requested by for the customer.
    • Perform evaluation of different simulation tools (fast-spice simulator).

    Additional AMS Modeling / Simulation Informations / Skills / Responsibilities:
    • Mentor Graphics AMS product line expert.
    • VHDLAMS modeling and the mixed top level simulations leader of many projects. Implementation of AMS simulation environment and modeling database delivery to design teams.
    • The good knowledge of AMS ICs verification flows (Top down/ Bottom up methodology).

  • Motorola Semiconductors, Toulouse (France) - Analog Design Engineer

    2002 - 2003 Position: Analog Design Engineer within WBSG / EMEA power management division.
    Job Description: To develop VerilogA/Verilog models for the validation of an ASIC for the 3G Mobile platform and perform top level simulations in collaboration with design leader.

    AMS Modeling / Simulation Experience:
    • Define top level simulation plans using a top down verification methodology. Write several stimulus in VerilogA language in order to check the behavioral of each macro-cell. (power, clock management, ADC …).
    • Develop behavioral models in HDL language. (Reference, biasing, clock management ….).
    • Develop and document the AMS ICs verification methodology.

    Additional AMS Simulation Informations / Skills / Responsibilities:
    • The knowledge of HDL language (Verilog / VerilogA / VerilogAMS)

Formations

Pas de formation renseignée

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