Mes compétences :
Gestion de projet
Electronique
C++
Entreprises
INFINEON/ INTEL MOBILE COMMUNICATION - Sophia, France
- PhD/Engineer Design for Manufacturing Methodology
2008 - maintenantPhD: Manufacturability and Yield improvement of integrated circuits for advanced technology nodes : 65/45/28nm
- Study of yield loss failure mechanisms
- Study of complete Place & Route flow using IC-Compiler from Synopsys
- Critical Area Analysis (CAA) using Mentor Graphics Calibre Yield Analyser
- Analysis of systematic defects: lithography simulations using Calibre LfD Mentor Graphics
- Development and implementation of a C++ automatic design data extraction tool through Open Access database
- Identification and definition of optimization criteria and margins for 45nm and 28nm circuits
- Definition and development of methods for lithography sensitive area prediction:
Behavioural Sensitivity Model detection of systematic defects( in collaboration with the company InfiniScale)
- Definition and development of layout correction techniques:
- Development of a routing decongestion tool
- Implementation of concurrent critical area (CA) and lithography improvement technique
ATMEL
- Engineer Training period: Test and validation engineer
Rousset2007 - 2007Engineer Training period: Test and validation engineer
- Development of an automatic electrical fault simulator for eFlash memory testing process
- Customer's specifications set up.
- Development of automatic memory test tool (C and Spice)
- Design of 90nm eFlash memory cells using Verilog-A and electrical simulation using Cadence
CNRS GLM of Marseille
- Company placement the neurobiology department of CNRS Engineer assistant in electronics
2004 - 2004Company placement the neurobiology department of CNRS Engineer assistant in electronics
- Design of a mobile electronic acquisition card
- Development of whole acquisition card hardware and software
- Development of driver and data-processing interface using Delphi
- Writing of technical documentation
Three years of PhD in microelectronics in collaboration with IM2NP french laboratory, Infineon and Intel Mobile Communications France.
PhD topic : Design for Manufacturing, Design for Yield, Design for Reliability, Place & Route.
Marseille2004 - 2007Master in Microelectronics & Telecommunications
Microelectronics and Telecommunications - Three years engineering programme. Multidisciplinary engineering course: Electronics / Computing / Design/ Communication Specialized in microelectronics
Génie Électrique & Informatique Industrielle - Paul Cezanne University (first two years after the Bachelor’s degree) Specialized in electronics and programming