Telnet
- Electronic Design Engineer
2009 - maintenant
Since October 2009
Presently an Electronic Design Engineer working on the Design of the Printed Circuits Boards (PCB) products in the Electronic Design Automation (EDA) division at Telnet; I am in charge of:
* The Analysis and Circuit Design, Schematic and Layout, BOM Creation, Technical Documentation, Optimization and Cost Reduction.
* The purchase of electronic components, planning with manufacturers and ensuring contacts with distributors in Tunisia and abroad.
* The start-up of the Electronic Boards Prototyping Line such as: Stencil-Printer Machine, Rework Machine, Pick & Place Machine and Reflow Oven.
* The purchase of the electronics components, organizing planning with the manufacturers and ensuring contacts with the distributors in Tunisia and abroad.
* The Analysis and Circuit Design, Schematic and Layout, BOM Creation, Technical Documentation, Optimization and Cost Reduction.
Projects:
• Plug-meter & Dongle (confidential customer): Re-Design, Schematic, BOM, Layout, Purchase of components.
• Netgem Set Top Box Decoder: BOM, Purchase of components, Manufacturing and Assembly of prototypes and Bring up test of prototype.
• Telnet Digital Terrestrial TV Set Top Box
• Power Analyser and Wattmeter of Chauvinx-Arnoux
• Terminal Display for a Navigation System (GPS) for automotive applications.
Integrated Circuits Used: STi5202 Decoder of STMicroelectronics, R8C/L38A microcontroller of Renesas
Telnet
- Analog IC Design & Layout Engineer
2007 - 2009
September 2007 to September 2009:
Analog IC Design & Layout Engineer
My task is to design the CMOS Analog Integrated Circuits by following the Analog Flow Design.
(Project Specifications, Requirements, Schematic, Sizing Transistors (CMOS Process), Simulation (Operating Point, Gain, Phase, Noise...), Layout (DRC, Extract, LVS), Post-Layout Simulation, GDSII, Layout Virtuoso, Diva, matching, Common Centroide, Analog Layout, Simulation Eldo & Spectre, Design of CMOS Operational Amplifier, Verification, DRC, LVS, Cadence, Checklists, Technology 0.5um & 90nm & 65nm..
Design of a CMOS Operational Amplifier : Front-end and Back-end
24 Bit Sigma Delta DAC for Audio Applications Project
Design and the implementation of the Analog part of 24 bits Switched Current Sigma Delta DAC used for audio applications.
Participate in the Digital Analog Converter project (CMOS process)
• Design of the Operational Amplifier.
• Review of the Back-end part of the DAC.
• Design environment is Cadence
• Simulators: Spectre, Spectre RF
• Layout: layout XL, DRC, LVS with DIVA
• Post-layout Simulation
CMOS Operational Amplifier, Cadence, layout XL, DRC, LVS with DIVA
Design and implementation of a Recovery Circuit Energy of a passive RFID Chip
Passive RFID ISO/IEC 15693 Project
Design and implementation of a Recovery Circuit Energy of a passive RFID Chip
Review of the:
• Design and characterization of : RF_Limiter, OTA, Bandgap
• Realization of the Ring layout for the test-chip RF
• Layout: layout XL, DRC, LVS with DIVA
• Post-layout Simulation
RF_Limiter, OTA, Bandgap, Cadence, layout XL, DRC, LVS with DIVA
Layout of CMOS Filter GmC
ALLOUIS Receiver - Mixer & Low Pass Filter - Project
This project focuses on the implementation of the analogue part of the receiver and especially the mixer and the low pass filter. These blocks are implemented in 0.5µm CMOS technology.
Back-end of CMOS Filter GmC
• Analog Design in technology: CMOS 0.5 µ
• Design of Mixer Block
• Responsible of the Back-end part of the Filter
• Layout: layout XL, DRC, LVS with DIVA
• Post-layout Simulation
Advanced training techniques of Analog Layout, cadence, layout XL, DRC, LVS with DIVA
Design and Layout of CMOS Ring Voltage controlled Oscillator
Start-up Project
• Control the MHS SCMOS3 0.5µm technology
• Identification of: technological parameters, models of transistors, topological rules and rules-electrical components of technology MHS.
• Design of Ring VCO with SCMOS3 0.5µm technology
• Training on the design of CMOS Analog circuits.
• Advanced training techniques of Analog Layout.
• Re-Design of the Ring VCO : Control Stage, Delay Cell, Buffer
• Layout of the VCO: Control Stage, Delay Cell, Buffer
• Layout: layout XL, DRC, LVS with DIVA
• Post-layout Simulation
Advanced training techniques of Analog Layout, VCO, layout XL, DRC, LVS with DIVA
Analog Design Flow
Analog Design in technology: CMOS 0.5 µm
Design environment is Cadence
Simulators: Spectre, Spectre RF
Layout: layout XL, DRC, LVS with DIVA
Post-layout Simulation
Characterisation: Gain, Margin phase, Noise, cut frequency, transition frequency, PSRR, slew-rate,
