STMICROELECTRONICS
- Ingénieur (Division Manager and Design team leader)
2006 - maintenant
Manage a team of 17 designers for the design of Analogue and Mixed signals IPs for All ST. The target is to provide AMS IPs solutions to ST community, with short cycle time, first silicon success & IP reuse, catering to the divisional needs.
• Design Team Manager (17 engineers)
• High speed link
• Audio activity
• frequency synthesiser Activity
• VHDL_AMS activity
• Digital team
• Implementation team
• Laboratory area to validate the blocs on chip.
Specialties:
Managment of people.
Project and program managment.
Design team Leader (Analog part PLL VCO ...)
Manage a team of 17 designers for the design of Analogue and Mixed signals IPs for All ST. The target is to provide AMS IPs solutions to ST community, with short cycle time, first silicon success & IP reuse, catering to the divisional needs.
• Responsible of Cost center (Budget).
• Manage human resource availability versus project needs according to the site mission.
• Ensure the availability of the adequate working environment according to the site mission, the project plan and the approved budget.
• Manage the training plan and the career path of the local team.
• Project management.
• Develop useful links and research programs with local schools and institutes.
• Enhancing R&D on Analogue design with local high engineering school.
• Set-up of ‘P.A.U.M’ ‘Pôle Analogique Universitaire Marocain’ Moroccan University Analogue Pole.
• Relationship between National Engineering School of Sfax, Tunisia and local high engineering school.
April 2004 – August 2006 (2 years 5 months)
• ST world wide Technical leader of Frequency synthesizer.
• Customers support.
• Roadmap of frequency synthesizer on all technologies.
• Developing new architecture.
• Manage of 5 engineers.
• Responsible of more Project of trainees from ( ‘EMI ‘INPT’ ‘ENSAT’ Morocco,’ENSERG’ ‘ENSI’ ‘Montpelier’ ‘Lille’ France, ‘ENIS Sfax’ Tunisia)
March 2003 – April 2004 (1 year 2 months)
• Analogue Design in technologies: 0,18 µ, 0,13 µ, 90 nm, 65nm.
• Design of fractional PLL and frequency synthesisers
• Low power and low noise designs such as: VCO, charge pumps, amplifiers, bandgap reference voltages, interpolators
• Knowledge on following STMicroelectronics’ process and flow: HCMOS8, HCMOS8S, HCMOS9, HCMOS9I, CMOS90, CMOS65
• Design with transistors LVT HVT SVT, High speed, Low leakage
• Design environment is Cadence
• Simulators: Eldo, Eldo RF, HSIM, Spectre, Spectre RF
• Layout: layout XL and Neocircuit, DRC, LVS with CALIBRE
• Post-layout Simulation: STAR- RCXT
• Characterisation and validation on test chip of PLL and frequency synthesisers (jitter, phase noise, consummation)
ENIS SFAX TUNSIE/ENSERB FRANCE PFE
1999 – 2002
Thesis National Engineering School of Sfax, Tunisia collaboration with ENSERB Bordeaux France
• Study of RF transceiver: Design of LNA 0.35µm for UMTS application.
High Gain Low Noise Figure CMOS Low Noise Amplifier for UMTS Application, M. H. Sbâa, S. Zouari, M. Loulou, A. Fakhfakh, N. Masmoudi - National Engineering School of Sfax, Tunisia. Northeast Workshop on circuits and systems NEWCAS 2003, Montreal, Canada, 17-20 June 2003.
