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Olivier PENNIELLO

Le Mans

En résumé

• Since 2013, Power IC layout development from top to cell level using TSMC130BCD technology, Cadence and Calibre tools

• From 2013 to 2002, 10 years of FULL TOP LEVEL LAYOUT development of Power IC layout with high integration (Power management, Audio, RF, USB, ADC) up to 40mm2, 300 pins/balls using Texas Instruments processes and tools.

• From 1999 to 2002, 3 years of ANALOG AND MIXED SIGNAL IPs development (USB, DCDC, LDO, RF Modules like VCOs,...)

++ Accomplishments : 20 Complex analog and mixed signal ICs
from 0.70 um to 90 nm technologies
++ Tools : Cadence VIRTUOSO XL
++ Applications : Smartphones – tablets - Modem products
++ Customers : Nvidia, Samsung, LG, Palm, Nokia, Motorola, Sagem, Amazon,...

• From 1995 to 1999
- 3 years as Lab and Test Engineer
- 1.5 years as Quality and Reliability Engineer

Mes compétences :
TSMC 130BCD tecnology
Floorplanning
automation using SKILL language
PCELLS Creation
Layout capability from top to transistor level
DRC, ERC, ANTENNAS, LVS Calibre and Assura checker
Layout Mixed Signal
Project management
Layout XL, Constraints manager, Wire assistant, VS
QFN, BGA, WLCSP Package
Lead

Entreprises

  • Dialog semiconductor - Analog Layout Team Lead

    Le Mans 2014 - maintenant

  • Dialog Semiconductor - Senior layout engineer

    2013 - maintenant Layout Lead on TSMC130BCD projects using Cadence 6.1.6 Layout tools for the developement and Calibre tools for verifications.
    Project management
    Package feasibility study
    Chip and Ip Floorplanning
    Power Ip layout.
    Top Lebel Routing.
    Electro-migration analysis & Parasitic extractions
    Tape out deliveries
    Cadence SKILL Automation
    PCELLS Creation

  • Texas Instruments - Senior Mixed Signal Layout Engineer

    Villeneuve-Loubet 1999 - 2013 MIXED SIGNAL TOP LEVEL SKILLS

     Leading of layout top devices
     Coordination of layout top activies from area (up to 40mm2 integration) study to mask delivery
     Schedule analysis until mask delivery
     Package / PinOut / BallOut study and feasibility up to 300 pins/balls (uBGA, single/multi-row QFN, WCSP)
     Floor-planning
     Digital box definition (form factor, pins placement)
     Module box definition - layout transfer to India team and follow up
     Top placement and routing
     BBox flow for early top layout verification (LVS)
     Top level layout verifications SIGNOFF (DRC, LVS, Antennas, Package)
     Parasitic extraction
     Tape out and masks verification

    MIXED SIGNAL IP LEVEL SKILLS

     Analog module placement and routing
     Analog constraints and techniques (matching, isolation, shielding, voltage dependencies)
     Module level layout verifications (DRC, LVS, Antennas)
     Simple digital macros

    LAYOUT TOOLS SKILLS

     CDB and OpenAccess (OA)
     Virtuoso Layout XL
     Open Access assistants (constraints manager, wire assistant,…)
     Automated procedures (Skill routines)
     Virtuoso Custom Router (VSR)
     Chameleon (DRC, Antennas checker)
     Assura (Package and LVS checker, WCSP, copper)

    FLOW PUT IN PRODUCTION TO REDUCE MARKET TIME

     Innovative floor-planning definition/partitioning
     Automatic and assisted routing techniques
     Development of layout automated tools (SKILL scripting)
     Development of Parameterized Cells libraries
     Cadence database management using versioning (Design Sync)
     EDA Support in collaboration with IT team
     Partnership with Cadence company for VSR tool improvement
    (Defect reviews and correctives actions put in production)

  • SYNERGIE CAD - Subcontractor @ TEXAS INSTRUMENTS

    1995 - 1999 Lab, analysis of customer returns

    Quality engineer, burn in qualification and analysis of customer returns

Formations

  • CNAM

    Nice 1998 - 2006 Master Degree

    Master Degree

Réseau

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