2003 - 2007Domain: E.D.A., Physical Verification
Roles:
Inventor of the technology core to reduce the complexity of large parasitic extractions of electronic designs.
IT and R&D manager (8 people). In charge of specifications, resources and working board management.
Management of external projects: European A.N.R. and regional MinaTec.
Startup creation and fund raising.
Implementation of the architecture and numerical computation libraries.
Products:
Jivaro (Netlist Reduction Platform)
Reduction of digital parasitic networks extracted by StarRC (Synopsis)
Reduction of analogue extractions extracted by Calibre XRC (Mentor Graphics)
Reduction of parasitic networks in OpenAccess from CADENCE layout extractions.
Reduction of analogue extractions for GoldenGate models (Agilent Technologies).
Projects:
Fast and accurate analysis of interconnect parasitic networks: Impedance, delay, voltage...
Patent:
“METHOD AND DEVICE FOR ANALYZING INTEGRATED CIRCUITS”, Europe WO2007051838 / 06807735.3
Cadence Design Systems
- Senior Engineer
Velizy Villacoublay2002 - 2003Deliver algorithms to reduce complexity of analogue and digital extractions for parasitic analysis.
Integration of linear system reduction algorithms in physical verification products: VoltageStorm, SignalStorm and SubstrateStorm; working with Worldwide Research Laboratories.
Simplex
- Staff Engineer
Москва2000 - 2002Development of algebra libraries to analyze parasitic extraction of electronic substrate.
Development and technology transfer to US of linear reductions for signal and voltage analyzers.
Formations
Institut National Polytechnique De Grenoble (INPG) (Grenoble)
Grenoble1991 - 1993PhD
Signal-Image-Speech - Thesis title: "Knowledge Base Systems For Oceanic Surveillance Support With a Magnetometer Network"
