Thomas LE HUCHE

En résumé

Entreprises

• STMicroelectronics - R&D Engineer

  2011 - 2014 Within “Reference Design Solution” team, I am currently working
  as a R&D engineer on critical parts of high performance HW
  design. Mainly I am responsible to bring solutions for clocking
  problems on high frequency and large ips, like in moderns multi-
  core and multi gigahertz application processors. The nature of the team and
  especially my work, has lead me to learn about and practice most of the design
  and verification steps of digital ips, from architecture and specification, RTL
  design, backend implementation and signoff verification. I had also to design
  some custom blocks in analog environment, to develop some drivers for one of
  our solutions (ARM Cortex-A7 based), or deal with bi synchronous dual voltage
  or asynchronous design parts. Very exiting experience, with a lot of challenges
  and success, where innovation and problem solving were the key points.

• Elsys Design - Verification Engineer

  Cachan 2010 - 2011 Contractor for a project of a cellphone application processor upgrade for STMicroelectronics, I have been taking part in several front-end duties and mainly verification: running non-regressions, simulation, HW/SW debug. Also I developed scripts for standardcells swap, and to reduce the overall compilation time. Lastly I was in charge of io-ring RTL generation. It was a good experience to increase my knowledge and
  global understanding of a complex system on chip, to work in a critical schedule
  context, with strong interdependence between all people involved. Verification
  was finished on time !

• Elsys Design - Architect Engineer

  Cachan 2010 - 2010 nvolved in the design of a cache memory for a video decoder, as contractor, my
  duty was to define a cache that will best match the requirements: Developing a
  generic model able to represent the different types of cache architecture &
  configuration, connecting it to an existing model of our decoder bandwidth,
  create an efficient environment to test all those cache configurations while
  decoding full HD H264 streams. Then I had to report and conclude about the
  study with the video architecture leader. Very interesting study and excellent
  results obtained in reducing by 70% needed bandwidth.

• Elsys Design - Verification Engineer

  Cachan 2009 - 2010 To change our video accelerator architecture, using High Level Synthesis (HLS),
  I have been in charge of setting up a new verification methodology to fit both with
  HLS and this architecture. Presentations and reviews of the methodology with
  architecture, design and verification teams to inform them about the impact of
  this methodology on their work. Preparing templates/macros/environments to be
  reusable in the whole front-end development flow. Demonstrating that the
  verification methodology is working for the current project, at IP level (DMA) and
  at top level (Video Accelerator).

• Elsys Design - Verification Engineer

  Cachan 2006 - 2010 As part of the video accelerator team for more than 4 years i have been in
  charge of many videos IPs unitary verifications, including test plan/spec review
  with architects, environments development (E/C/RTL/csh), debug, coverage
  analysis, and environment qualification with fault injections in the design.

Formations

• Polytech'Nice Sophia-Antipolis

  Biot 2001 - 2006 Masters Degree

Réseau

• Alain WITTMANN