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AREVA
- Hardware Design Engineer
Paris La Defense
2014 - 2015
Designing a CAG; serial input (RS232) serial output (SPI) for DACs.
Generated Document specification and test procedure document.
Libero SoC v11.3 Microsemi, Modelsim ME 10.2c.
Designing an input stream decoding module (ASCII) for configuration: synthesizers components.
DACs components, CAN and GPIO components. Generated design in VHDL for FPGA and Xilinx SPARTAN6 VIRTEX6
Generated VHDL for FPGA design in ACTEL A3P125
Use numato LAB evaluation board.
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Thales Avionics Electrical Systems
- FPGA Verification Engineer
2012 - 2014
Develop a functional verification plan DO254 DAL-A for two Actel FPGA A3PE3000.
Collaborate with documentation requirements to make responsible verifiable requirements and improve the code coverage.
Write a document requirements verification procedures
Modeling components (datasheet) that allow to emulate the FPGA to test.
Write the test bench (VHDL + tcl) with traceability between test results and requirements.
Tools: Doors, Microsemi, Modelsim SE6.6, ARINC 429, Ethernet bus, SPI, Special Serial Link.
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sensorex MEGGITT
- Hardware Engineer
2012 - 2012
IMU Qualification test (Inertial Measurement Unit) for DO254 certification level B.
Writing test procedures HTP (Hardware Test Procedure).
Make the requirement for skills tests on normal test bench or on a specific bench (temperature, vibration, acceleration ...)
Write test results in an HTR (Hardware Test Results).
Rectify, Logic analyzer, oscilloscope, specific test bench (temperature, vibration on three axes) for calibration.
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Thales Airborne Systems
- Verification Engineer
Courbevoie
2011 - 2011
Implementation of Radar Signal Processing.
In the context of a system receiver Broadband Instant integrating the level measurement of a signal sample.
Develop measures sampled in time level continuously corresponding to the total received power RF input.
Acquisition of analogue signals / 16-bit ADC
Digital low pass filtering coefficients rechargeable
Treatment of the calculation algorithm of the signal strength
Acquisition of configuration parameters and algorithm parameter tables by fast serial link fiber optic GTX
Intermediate result in the acquisition processing chain by the algorithm speed serial link over fiber GTX
Implementing the protocol AURORA Xilinx
VHDL, Xilinx Virtex6 (XC6VLX240T), XST / ISE 12.3 and ModelSim ML605 evaluation board.
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Thales Avionics
- FPGA Verification Engineer
2010 - 2010
Update testbench for functional verification and post according to changes in the requirements documents.
Test bench in VHDL (ModelSim).
Development and realization of the conduct of test scenarios on simulation platform.
Validation of code coverage (SECO) 100%
Report Writing test results, as required by the DO-254 DAL A.
Tools: Unix, DOXYGEN, VHDL, CPLD ACTEL ProASIC3, MODELSIM.
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Orange Labs
- Design Engineer
Paris
2010 - 2010
Home Automation and Communications Protocol Networks
In the context of a European project with the laboratory "Wireless Indoor" of Orange
Labs, for making a prototype optical wireless infrared communications (IR) and visible light (VL) with flow rates of 100 Mb / s and 300 Mb / s:
Design and implementation of a communication protocol based on the detection and management of frames in the order of arrival:
Generated VHDL for FPGA Virtex 5
Setting up a test bench for verification of a network protocol to three modules.
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Thales Communication
- Hardware Development Engineer
2009 - 2010
Electronic board validation and FPGA Design
* Design two CPLD (sequencing of the power regulators) using VHDL.
* Implement a procedure and generated VHDL for validating an electronic card that includes:
3 FPGA ALTERA cyclone and 1 FPGA ACTEL, SDRAM, FLASH, PIC and, µP.
* VHDL design of a secure communication interface of a Cyclone FPGA 3 and a soft interface (NIOS II) with the Personal Computer.
Design and development of hardware modules around the Avalon bus.
Design and real-time Driver Development (communications serial link RS 232)
Tools: FPGA ALTERA Cyclone III, SOFTCORE NIOSII, Quartus II, ModelSim, Actel, Lattice ISPLever and lab test equipment
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Thales Avionics
- Verification Engineer
2009 - 2009
From an existing design (A400M) and take into account the adjustments conform to the requirements A350 product design. in e context DO254 DAL B.
CAN, EEPROM, interface.
Generated VHDL for FPGA ACTEL Pro ASIC 3
Tools: LIBERO8.4, DESIGNER, MODELSIM
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Thales Communications
- FPGA Design Engineer
Courbevoie
2007 - 2009
Improved channel pulse detection of a radar detection system (IFF).
Design in VHDL on FPGAs Xilinx the emission part of the new system for radar detection IFF Mode 5.
Design, functional verification, synthesis and implementation.
Tools: XST ISE, FPGA Virtex, Modelsim, DO254, and lab test equipment
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IXSEA
- FPGA Design Engineer
2005 - 2005
New product for underwater positioning, development of logical pre-processing of
acoustic signals, interfacing with a DSP (Free scale) and communicating with a PCI Master / Target 32-bit 66 MHz On FPGA Xilinx SPARTAN 3
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Actaris
- Design Engineer
2004 - 2004
Feasibility study and implementation of a model for the wireless meter reading
Search for existing solutions in the field of wireless communications
Study of solutions based on programmable devices or microcontrollers
Tools :MPLAB ICD2 Micro chip, Language C
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Artus
- Hardware Design Engineer
2004 - 2004
Aeronautics, ARINC 429 bus, QTP - ATP on specific bench, Power Switches Command & Control
Debugging and optimization of logic control and monitoring of a power converter AC / DC 6KW
on Xilinx to manage multiple micro cut on the power bus.
Design on a new FPGA integrating monitoring function with news functions (recording of failures in EEPROM memory).
Tools: XST ISE and Actel, Visual Elite, Leonardo, Synplify, Modelsim, ARINC429, and lab test equipment(qualifications tests).
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Schneider Electric
- FPGA Design Engineer
Rueil Malmaison
2003 - 2003
Design of control software of an electronic power converter DC-DC (100KW type Double-Boost
four levels) for an application such as embedded energy (fuel cell). This software provides the functions of safety,
regulations and control of the IGBT from acquiring and processing electrical data on FPGA Xilinx.
Tools: XST ISE, SPARTAN, Modelsim, and lab test equipment.
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Mitsubishi
- FPGA Design Engineer
Paris
2002 - 2002
For communication between the boards compatible with LVDS channels with channels
serialization / deserialization 10:1-1: 10 from National Semiconductor, collect a stream of asynchronous FIFO
clocked by a clock 33,33MHz to serialize a rate of 400 Mbps on Xilinx FPGAs.
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Thales Airborne Systems
- Design Engineer
Courbevoie
2001 - 2001
Development of interface modules with a DSP, a bench test vector generator and digital signal
pre-processing.
Tools: Unix, Xilinx, VME, RS 232, Leapfrog, Cadence, and lab test equipment.
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MATRA BAE DYNAMICS
- STAGE
2000 - 2000
