Vélizy-VillacoublaymaintenantDesign For Test engineer, OMAP Platform (90nm) project at Texas Instruments
• Development of a Scan Combiner Module, activating all the scan chains of the chip and allowing their access from the chip border
Write specification files (functional, design and integration specification)
VHDL coding + testbench writing
Design Compiler Based Synthesis
Top level validation
• In charge of the Efuse_farm module, consolidating all fuses for the chip into a single block. The Fuse_Controller reads fuse data from a FuseROM and serially shifts the data out to the rest of the chip.
Write functional specification file
VHDL coding of the efuse_farm wrapper
Design Compiler Based Synthesis
Top level validation
• Development and validation of several small test modules
Burn In monitor module
BSC_module: Boundary Scan Chain management of big Hardmacros
• Definition of the Burn In Activation Specification (process used to accelerate device failures through application of stress temperatures and voltages for prolonged periods of time in a production test environment)
• Verification of fault coverage and test coverage (use of Fastscan) for stuck-at faults and transition faults. Debug and analysis of the results. Write scripts in PERL language to automate the flow.
• TDL (Test Description Language) files writing
Altran Mediterranee
- DFT Engineer
Vélizy-VillacoublaymaintenantDesign For Test engineer, OMAP Platform (65nm) project at Texas Instruments
• Development of a PLL Combiner module providing:
A programming interface for ADPLL through mapped top-level JTAG accesses
Status information on ADPLL operations
Frequency measurement capabilities in Go/NoGo fashion
Short-term jitter measurement capabilities
Write specification files
VHDL coding + testbench writing
Design Compiler Based Synthesis
Top level validation
• In charge of the Memory Data Path structures allowing routing address, data and control signals from top-level PBIST controller to all intended memories and also routing memory outputs to PBIST controller and gating control signals based on PBIST controller outputs.
Write functional specification file
MDP generation + VHDL coding of the MDP wrapper
Design Compiler Based Synthesis
Top level validation
• TDL (Test Description Language) development plan writing
Altran Mediterranee
- DFT Engineer
Vélizy-VillacoublaymaintenantDesign For Test engineer, Imaging SubSystem (45nm) project at Texas Instruments
• In charge of the DFT specifications:
Review the DFT guidelines defined by top level DFT team
Interface with top level DFT team to define the best DFT strategy to be applied (specific strategy defined for ISS sub-system containing a huge number of scan chains)
Collect all memory information:
For Memory Data Path (MDP) groups definition
For fuse number computation
• Review all ISS sub-modules integration specifications:
Verification of entities and test signals
Review all clock and reset trees
• Support for former IP projects:
ATPG test patterns generation using an internal flow (based on scripts) and simulation with Fastscan, on new netlists
Test patterns delivery
Altran Mediterranee
- IP Design enginerr
Vélizy-VillacoublaymaintenantDesign For Test and IP Design engineer , Dynamic Memory Management IP (45nm) project at Texas Instruments
• In charge of ROBIN module (Re-Ordering Buffers and Initiator Node) a block aimed at providing some working buffering for converting data and responses to-and-fro between raster and sub-tiled organizations and for reconstructing bursts spanned on the two memory controllers; it is also an OCP master port to connect to the SDRAM controllers:
Review the functional specifications
Define a structured architecture for ROBIN: 1 sub-module per each phase (Request, Datahandshake, Response) + 1 module for Management for Write Context and 1 for Management for Read Context)
Code development with Esterel Studio
Check auto-assertions (single signals, read-before-write, out-of-range)
Simulation and debug with Esterel Studio tool
Work in parallel with Formal Verification and Specman Verification teams for bug analysis and correction / Run local regressions and interactive simulations with Specman tool.
Timing improvement for the main critical paths
• In charge of the OCP rtl.conf file:
Define all OCP interfaces (masters and slaves) and their parameters based on the functional specifications
