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Nadege SIUTRYK

ZURICH

En résumé

Electronics engineer from Polytech' Sophia, I have been willing to concentrate not only on the hardware but also on the software side, convinced that it would give me a better overview and understanding of the development flow. This is the reason why, after having spent several years on getting a hardware design experience, I had chosen to widen my technical skills with embedded software development.

Eager to take up challenges, I am currently looking for a new position to better fit my aspiration.
My past experiments have allowed me to build strong knowledge on the technical aspect and to develop my analysis and methodological capabilities.
Today, I would also like to give an important place to the exchanges with the different stackeholders and develop my soft skills as well.
Thus, I am looking for a position which requires both technical and soft skills and that better fits my personality.

Entreprises

  • Schmid Telecom - Firmware Engineer

    2011 - maintenant Zurich, SWITZERLAND

    Embedded software development for SHDSL modem (Ethernet in the First Mile (EFM)):
    • Implementation of standardized MIB (Management Information Base) objects related to Stacked VLAN, Link Aggregation, Regenerator: understanding of standards and MIBs, C++ coding

    • SNMP access for modem management (access to MIB objects)

    • Bash scripting for Command Line Interface (CLI) implementation for user interface

    • Tests development for CLI and MIB objects: Python coding

  • ST-Ericsson - Development Engineer

    2007 - 2011 Zurich, SWITZERLAND

    • Responsible of DFT for several modules (for baseband chips), among which: Clock Generation Unit, Image Subsystem, USB
    -> DFT insertion and validation, scan compression, test implementation and simulation

    • In charge of Memory BIST (Built In Self Test) for different subsystems:
    -> BIST definition and ordering and implementation at RTL level (use of Spyglass)
    -> Top level verification (RTL and gate level): simulation of testbench (JTAG accesses) to program and run BIST on both RAM memories and ROM memories (signature checking)

    • Development from scratch and validation of Memory Redundancy Controller module, allowing the compatibility between the EFuse Macro Cell (storing repair information) and Memory BIST system:
    -> write functional specification file, definition of FSM, Verilog coding, top level verification (RTL and gate level simulation) simulating faulty memory case and repair case

  • Texas Instruments - Design For Test Engineer (Contractor)

    Villeneuve-Loubet 2006 - 2007 Villeneuve Loubet, FRANCE

    Design For Test Engineer (Contractor)
    • Development and validation of several test modules (for a modem chip), among which: Burn In Monitor and also PRCMBIST (module to check clocks and clock enables paths that are not covered by standard ATPG):
    -> write functional specification file, VHDL coding, synthesis, top level verification (RTL and gate level simulation)

    • Verification of fault coverage for stuck-at faults. Debug and analysis of the results

  • Philips Semiconductors - Design For Test Engineer (Contractor)

    Suresnes 2005 - 2006 Sophia Antipolis, FRANCE

    Design For Test Engineer (Contractor)
    In charge of DFT scan, for a modem chip:
    -> scan flip flops insertion (to create one or more scan chains), test patterns generation (to generate sequences of test patterns with stimulis and expected answers to test a module), testbench creation (to validate and simulate the patterns at the IP level), simulation at gate level

Formations

  • ESINSA - EPUNSA - ECOLE POLYTECHNIQUE

    Biot 2000 - 2005 Polytech Nice Sophia (Ecole Polytechnique Universitaire de Nice Sophia-Antipolis)
    Master, Electronics Engineering
    Specialization in Microelectronics
    Top of the year

Réseau

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