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Cadence Design Systems
- Leads Application Engineer
Velizy Villacoublay
2012 - maintenant
Supporting Tempus (Static Timing Analysis) and Voltus (Signoff Power integrity) tools.
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ST Microelectronics
- Digital design engineer
2007 - 2012
-Timing Analysis and timing constraints management for SOC projects.Using Synposys PrimeTime, Synopsys Galaxy Constraint Analyser, Cadence ETS.-Synthesis (Synopsys Design Compiler)-Clocktree management.-muti sites projects (India, UK, USA)
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ST Microelectronics
- Physical Implementation Engineer
2003 - 2007
-Physical Implementation designer. In technologies cmos 90nm, 65 nm, 32nm.Block and Top levels.Follow up of sub-blocks designers.Tools: Cadence Encounter, Synopsys Astro, Mentor Graphics Calibre.
