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Laurent CHARLES

Paris

En résumé

I am currently working at a French research laboratory located in Strasbourg (CNRS/IPHC) since december 2005. My area of work is the development of data acquisition systems for Particle Physics (CERN notably) and Nuclear Physics using high-speed digital electronics and new generation of programmable components (FPGA). I have extensive knowledge of FPGA design in VHDL (modelling of complex architectures, simulation, interfaces integration, implementation and verification). I am familiar with the hardware design (choice of components, schematic) and with the software development (definition of the registers and memory-map, scripts writing). I have a strong background in the implementation of several functionalities into the FPGA:
- > High-speed serial I/O (Gigabit Ethernet, USB2)
- > High-speed optical link (SFP+, GBT protocol)
- > Memory interfaces (DDR3, µSD)
- > High-speed ADC data management (de-serialization)
- > DSP algorithms notably for nuclear spectroscopy
- > Slow control (SPI, I2C)

Mes compétences :
VHDL
FPGA
High-speed
C
Nuclear Instrumentaion
MATLAB

Entreprises

  • CNRS - Engineer in Digital Electronics FPGA/VHDL

    Paris 2014 - maintenant Project Ex2 in Nuclear Physics
    - Development of a complete μTCA DAQ allowing the acquisition of Germanium detectors (10 channels) for students
    - Integration on the μTCA GLIB board + Mezzanine FMC112 from 4DSP Inc. (12 channels / 125 MHz)
    - Firmware development (VHDL) for Virtex-6 (de-serialization of the ADC data, automatic alignment, trigger and energy computing, registers and memory- map definition, etc.)

  • CNRS - Engineer in Digital Electronics FPGA/VHDL

    Paris 2013 - maintenant CMS/CERN – Pixel Upgrade – Collaboration with CMS Austria
    - DAQ – Pixel readout
    - Goal: replacement of the current Pixel Front-End Driver (PixFED/VME-based)
    - Integration on the μTCA GLIB board + FMC mezzanine with SFP designed by the CERN
    - Test to perform in the next few months: acquisition & readout of about a thirty coded TBM (Token Bit Manager) serial data flows
    - VHDL design of a test bench emulating the TBM data flow in emission (user encoding, 4b/5b encoding, 400 Mbps serialisation, etc.) and in reception (400 Mbps de-serialisation, 4b/5b decoding, user decoding, etc.)

  • CNRS - Engineer in Digital Electronics FPGA/VHDL

    Paris 2012 - maintenant CMS/CERN – Traker Upgrade – Electronics for 2S & PS-Pt Modules
    - DAQ – Silicon microstrips readout
    - Goal: replacement of the current Front-End Driver (FED/VME-based)
    - Integration on the μTCA Gigabit Link Interface Board (GLIB/Virtex6) developed by the CERN
    - VHDL design of the all DAQ chain
    - Acquisition/I2C configuration of CBC chips (CMS Binary Chip from CMS UK)
    - Data packing + Gigabit Ethernet readout through the UDP/IPBUS protocol
    - High-speed optical link (SFP+/4.8 Gbps) between the Front-End GLIB(s) acquiring the CBC data and the Back-End GLIB performing the readout
    - Commissioning modes added useful for calibration of the CBC chips
    - Trigger throttling management
    - Writing of the registers and memory-map (FW / SW)
    - Test scripts in python + Interface with xDAQ, the CMS online software
    - SVN storage and technical reports in English shared for all the collaboration
    - Successful beam tests
    -> CERN/Oct. 2012 – Test of 1x CBCv1 module with CERN constraints (TTC the Time and Trigger Control, TTS the Trigger Throttling Control, etc.)
    -> DESY/Nov. 2013 – Test & qualification of 2x Dual-CBCv2 mini modules through 2 GLIBs in acquisition optically linked to 1 GLIB performing the readout – Arrival time estimation of the trigger by TDC
    - Member of the Tracker author list

  • CNRS - Engineer in Digital Electronics FPGA/VHDL

    Paris 2009 - 2011 Bio-logging: miniaturized bio-loggers for the tracking of animals living in harsh environments (penguins, turtles, etc.)
    - FPGA Prototyping of a bio-logger addressing up to 10 digital sensors by SPI or I2C (luminosity, accelerometer, temperature, etc.) through the Spartan-3 development board from Opal Kelly
    - VHDL implementation (wake-up control, acquisition in parallel, storage in μSD memory, RS232 readout, etc.)
    - Choice of the digital sensors from different vendors
    - Tests and verification
    - Participation to the writing of the French-Chinese ANR “PEDALO”, a call for funding for the design of a new ASIC-LOGGER reducing drastically the power consumption and increasing the deployment duration
    - Supervision of a Chinese Post-Doctoral student
    - Project not completely completed (end of collaboration with biologists)

  • CNRS - Engineer in Digital Electronics FPGA/VHDL

    Paris 2006 - 2009 European Project “AGATA” for gamma-ray spectrometry in Nuclear Physics
    - Design of the Digitiser (36 channels /14-bits/ 100 MHz)
    - VHDL description of digital algorithms to characterize precisely the gamma energy (Baseline Correction, Trigger, Deconvolution, Pole-Zero Computing, Time Over Threshold estimator by TDC, etc.) and implementation into FPGA Virtex-2Pro
    - Implementation of the interface to the PC (Xport/Ethernet + A32/D32 communication
    - Tests and verification of the manufactured cards
    - Technical documentation in English
    - Firmware of the PSG (Pulse Shape Generator) allowing to emulate the output of a detector from AGATA
    - Publication co-author: Nuclear Instruments and Methods in Physics Research A 668 (2012) 26–58

Formations

  • Blaise Pascal University

    Clermont Ferrand 2002 - 2003 Master's Degree (DESS / Master 2 Professionnel)

    Marks: 14.75/20
    Programmes: Design of analog and digital ASIC, VHDL, Cadence, Microelectronics process

  • University Henri Poincare

    Nancy 2001 - 2002 Master's Degree (DEA / Master 2 Recherche)

    Marks: 12.55/20
    Programmes: VHDL design, FPGA Altera, Algorithm-Architecture Adequation, Microelectronics (IC Design & Process)

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