Nokia Mobile Networks
- Design Verification engineer - 5G Layer-1 Uplink Front end
Technique | Nozay (91620)2018 - 2021During 1 year involving 2 people :
- Performed Top level verification of 5G Layer-1 Uplink FE for an internal 5G phone emulator
- Contributed to building and updating a SystemVerilog UVM based testbench
Since then, involving 15+ people :
- Top level verification of 5G BTS L1 UL FE with quite same UVM environment, now reusing IP verif
- Adding new features, updating and maintaining the enviromnment
Simulations are executed on Mentor Questa Core & Synopsys VCS simulator tools
One of the key people within the verification team · Led a small team of 5 subcontractors
Nokia Mobile Networks
- FPGA Design engineer
Technique | Nozay (91620)2017 - 2018· Integration of 3rd party LDPC decoder IP for 5G Layer-1 Baseband NextGen ASIC:
- design of a codeblock data feeder/ Transport block data extractor,
- synthesis : resource optimization, Timing analysis, perf. comparison : throughput, latency, speed
· Re-design / optimization of existing internal CPRI core IP
· Design of an AXI4-Full feeder used in the VHDL testbench for 5G Downlink FE
Safran Electronics & Defense
- Ingénieur développement FPGA
PARIS2016 - 2016Division Optronique et Défense
Stage : diffusion par FPGA d’un flux vidéo HD non compressé sur réseau Gigabit Ethernet
Safran Electrical & Power
- Ingénieur développement FPGA
2015 - 2015Division Power - centre aéronautique de Réau
Stage : Cartographie des modules FPGA/DSP et réalisation d'un design FPGA pour une application de contrôle-commande moteur
FLIR Systems
- Assistant ingénieur électronique - en apprentissage
Issy les Moulineaux2011 - 2012Étude et développement en rev.B d’une carte de numérisation vidéo
SYLUMIS
- Opérateur Test - intérim
2010 - 2011Test et/ou reprogrammation de dalles de lumières LED
