Milpitas
IC Layout Engineer with experience in Analog and Digital layout in 800nm, 500nm, 450nm, 250nm, 180nm, 130nm, 90nm, 65nm, 55nm, 45nm, 40nm and 28nm CMOS technology.
- Floorplanning, toplevel routing, layout of all sizes of layout cells, blocks chips.
- Layout verification & robustness with Dracula , Assura, PVS and Calibre (DRC, ERC, LVS, ANT, PEX, LPE, DFM, ESD&latchup, Electromigration).
- Implementation Library I/O Pads structures / BondPads
- Backend support to prepare ICs for tape out.
- Customised the development tools to enhance the productivity of the team.
- Testing and coaching for new tools ( Cadence ), participating in flow and procedure refinement.
- Communications within group, outside group and through large time zone differences.
- Training new hires and junior team members.
- Writing and giving analog layout training material and course.
Pas de formation renseignée
