Velizy Villacoublay
Product Engineer at Cadence Design Systems: (14 years)
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Customer support for product still in development (Beta phase), visits customers to deliver demos on new product, trains Application Engineers on new product and writes specification for new tools on these specific areas:
- Flow:
*In Virtuoso (Physical Design)
*Interoperability between Virtuoso and Encounter on Open Access (OA) 2.2
*Interoperability between Allegro Package Design (APD) and Virtuoso on OA2.2
- CIC (Custom IC):
*Virtuoso Floorplanner on OA2.2
*Virtuoso Preview
- ICD (Digital):
*Floorplanning
*Power Planning
*Power Routing
*Place & Route
Backend Leader at ST Microleectronics: (3 years)
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Designs chip at physical level, manages project and ressources specific to this project, communicates with Front-End designers and with Program Managers for teh following chips:
- 4 Power Managers chip on 0.5u:
*Project lead at Backend Level
*Floorplanning
*Top Level placement and routing
*Physical Verification LVS, DRC and ERC
*Packaging verification
- Analog Cells: LDOs (Low Drop Out), BandGaps, Pads, etc...
- RF: BufferLos, LNAs, Mixers, Pads etc...
Specialties:
Flow development for Physical Design Tools from the Layout tools to the physical Verification tools via Packaging tools. I can cover the full flow for Custom Physical Design with also some Digital layout expertise.
