Arthur FREITAS

En résumé

Entreprises

• Freescale - Design Verification Engineer

  Toulouse 2011 - maintenant Led the verification efforts of a battery monitoring SoC.
  
  Developed a metric-driven methodology to address top-level verification of mixed-signal ICs.
  
  Defined verification plan in cooperation with Chip Lead.
  
  Developed automated self-checking testbenches using UVM.
  
  Developed and validated high-performance behavior models using Verilog-AMS (and its wreal subset).
  
  Developed a methodology to verify Verilog-AMS models against schematics / Spice.
  
  Developed mixed-signal assertions to ensure the proper functionality of analog sub-blocks at SoC level.
  
  Developed customized net disciplines and connect rules allowing the mix and match of real-number and transistor-level models in simulation.
  
  Developed a methodology to correlate behavior models with schematics

• ST-Ericsson - IC Design Engineer

  2007 - 2011 Responsible for top-level verification of multi-mode 45nm RFCMOS transceivers
  
  * Planned and executed top-level verification
  
  * Developed simulation environment and testbenches
  
  * Wrote checkers, bus functional models and assertions using verilog, systemVerilog, and PSL
  
  * Created models for analog and mixed-signals blocks using verilog AMS
  
  * Designed calibration and pre-burst setup sequences using assembly language
  
  * Modeled different on-chip power domains using Common Power Fromat (CPF)
  
  * Generated verilog netlists from schematics to perform top-level AMS simulations

• Hyperstone - Development Engineer

  2005 - 2007 Responsible for design and verification of flash memory controllers
  
  * Accelerated design and verification environment of a flash memory controller by a factor of 200 with integration of a microprocessor C-model in logic simulation
  
  * Substantially improved the overall development of flash memory controllers by conceiving and implementing a hardware/software co-verification environment
  
  * Conceived and implemented regression test suites in C and assembly language to verify microprocessors and flash memory controllers
  
  * Automated the compile and simulation flows using script languages, such as perl, TCL/TK and bash significantly improving the productivity of the design team
  
  * Used PSL and SystemVerilog to improve verification through assertions and also to provide functional coverage metrics
  
  * Created scripts for the logic synthesis and scan insertion of flash memory controllers

• Philips Semiconductors - Development Engineer

  Suresnes 2002 - 2005 Responsible for logic design and synthesis of TFT LCD controllers
  
  * Designed and implemented a decoupling FIFO to interface the input/output video pipeline of a TFT- LCD controller chip
  
  * Implemented and executed the logic synthesis and scan insertion of a 600K-gate chip in cmos18 for 166MHz
  
  * Performed static time analysis for a 600K-gate chip
  
  * Supported laboratory group in chip validation by performing power measurements and characterization tests
  
  * Performed sign-off gate-level/SDF simulations of entire chips before tape-out

Formations

• Grenoble Ecole De Management

  Grenoble 2010 - 2012 Master of Business Administration (MBA)

• Hochshule Furtwangen (Furtwangen)

  Furtwangen 2000 - 2002 Msc Microsystems Engineering

• Universidade Federal De Santa Catarina (Catarina)

  Catarina 1994 - 2000 BSc Electrical Engineering

Réseau

• Alix BIDAINE

• Benoît CONTI

• Brigitte SCHERRENS-DA SILVA

• Camille CLAUZEL

• Cédric LABOUESSE

• Jean-François GUILLON

• Jézabel DUBOIS - LUSSEAU

• Lamar WILLIAMS

• Nathalie MASSAT