Mes compétences :
Architecture
Design
Gsm
MPEG4
Soc
System architecture
Entreprises
NXP -founded by Philips, Crolles2Alliance
- Digital Designer
2006 - maintenantWorking in a team for library qualification and process calibration of the 65nm and 45nm technologies.
Responsible for the functional validation ,STA and test patterns generation for silicon validation.
Participation in the bonding diagram creation.
Responsible of the desing, synthesys,front end and back end validation of digital functional blocks.
Responisble to establish a complete flow for synthesis of a digital block. Target of different area, frequency, and libraries.
EASII- IC
- Digitam IC Designer - consultant
2004 - 2006Working as consultant in diffrenet enterprises:
ST, Grenoble, (3-month duration)
-Project NOMADIK: a multimedia application processor based on
the ARM9 processor.Collaborated with the system level
verification team.
-Development of test vectors in C, simulation and
verification
-Development of interfaces for test in VHDL and Verilog
EASII -IC, Grenoble, (4-month duration)
Project Internal IP development
-Designed the architecture and implemented the RTL in VHDL of
a CAN2.0 B controller
-Developed a generic memory interface in LabView
-Designed in LabView a functionality improvement of an
existing 12-bit Analogue/Digital Converter interface
PHILIPS SEMICONDUCTORS, Sophia-Antipolis, (4-month duration)
-Project TARA2: a Bluetooth baseband controller, based on an
ARM7-TDMI and a Bluetooth core, supporting EDR (Enhances
Data Rate). Collaborated with the system level verifcation
team.
-Responsible for system level RTL and gate level simulations
for the: low power mode, voice exchange interfaces, RSSI
(Received Signal Strenght Indicator) and access to the
Bluetooth RAM
-Designed verification tests in LAZY (Philips proprietary
language) and assembler for TARA2
-Designed tests for the verification of the Bluetooth core
WAVECOM
- Digital IC Designer
Issy les Moulineaux 2002 - 2004-Participation in the definition of the internal RTL coding design rools.
-Project WHAT3+ :GSM/GPRS station. RTL design(Verilog) and verification of a DMA controller.
-Project WHAT5: SoC baseband GSM/GPRS/EDGE multimedia, based on ARM926-EJS.
-Responsible of a 2D graphic accelerator:
-Research of algorithms for « line draw »and raster
operations, alpha blending and affine transformations on 2D
objects;
-Architecture design and specification of the accelerator;
-RTL design (Verilog) and design verification with SPECMAN
models
-Test of a multi standart camera interface using SPECMAN models.This interface provides functionalities of clipping, downsize, RGB and YUV convertors, rotation, flip of images.
-Verilog RTL design and test: upgrade of a keyboard module; design of a GSM Encryption Algorithm for GPRS; design of a register interface for a SIM card controller.
-Responsible for the system level integration and verification using C of the following modules: AHB NAND-FLASH controler, using DENALI memories models of 8 and 16 bits; I2C Designware IP.
Philips Research France
- Research engineer
2001 - 2002Working on two projects:
-Stream Architecture eNgine Dedicated to Real-time Applications (SANDRA). Study of algorithms for 2D,3D and video MPEG4. Definition of the functional units architecture.Definition of the communication protocol between these units.
-MPEG4 renderer - Development of a hardware accelerator for MPEG4 rendering for mobile applications.
