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Christine DUBOIS

En résumé

Forte d'une expérience de 9 ans en gestion de projet, j'ai réussi en Février 2015 la certification PMP.

Mes compétences :
Chip development
competition analysis
Verilog
Responsible for technical coordination
Responsible for quality insurance
Responsible for overall program management
Program Management
Microcontrollers
Integrated Circuit
Customer Support
Business Development
ASIC

Entreprises

  • EM Microelectronic - Program Manager

    2016 - maintenant
  • Scaleo chip - Program Manager

    2006 - 2015 SoC Development Program: up to 5 Million Euros / up to 250 MM
    * Responsible for overall program management, coordination, and consistency checking;
    * Establish the development plan; actively keep track of the defined schedule during the program execution. Follow key milestones and implement corrective actions if necessary;
    * Follow up the suppliers as well as internal development activities;
    * Customer official contact point;
    * Report on the progress and success of the program; Organize progress reviews with the customer;
    * Ensure compliance with contractual requirements;
    * Responsible for quality insurance;
    * Coordinate project documentation delivery; ensure the compliance between initial requirements and program deliverable.
    Collaboration - Partnership - Business Development
    Scaleo chip research areas are supported by cooperative programs funded by French clusters (systematic, CIMPACA, CAP Energies) or European ones (ARTEMIS, ITEA, European FP5 founding programs). Scaleo chip is involved in several research programs to improve the design flow of ASIC and ASSP.
    Responsibilities: Coordination of research programs both National and European levels (each program around 1M EUR budget / 100MM)
    * Progress report towards founders ;
    * Responsible for technical coordination and communication between partners ;
    * Engineering team management, Supervising PhD student ;
    * Participation in progress meetings, Reporting activities ;
    * Management of the development plan ;
    * Registering Scaleo chip in future research programs ;
  • Scaleo chip - Field Application Engineer

    2005 - 2006 * Provide Technical Support to customers on company products (the Teletext System-on-Chip family and the company design methodology using proprietary emulation and prototyping platform).
    * Assist the sales team in the identification of future customers, prospecting, response to RFQ, Elaboration of quotations.
    * Marketing activity: competition analysis, contribution to the development of business model.
  • Scaleo chip - Teletext Project Manager

    2003 - 2005 * Supervision of systems engineers in charge of software development and product validation in the design of "system on chip" based on ARM7TDMI core. Digital TV application - Teletext.
    * Customer Support to ease sales and production ramp-up. Travels in Asia (China / Japan).
  • Scaleo chip - IC Design Engineer

    1998 - 2003 * Mastering the complete design flow of integrated circuits: modelling in verilog language, usage of the SYNOPSYS tool suite for synthesis to target 0.35μm technology, generation of test vectors, achieve fault coverage objectives, scan integration, simulation under ModelSim/MENTOR, pinout and package definition, product specification, utilities from foundry partners (memory generators...).
    * Responsible of the FPGA synthesis (ALTERA devices) with the objective to deliver to automotive customers an emulation platform which behaves as the targeted ARM based microcontroller.
  • ATMEL - Analog Design Engineer

    Rousset 1997 - 1998 internship * Analog to Digital Sigma-Delta converter

Formations

Réseau