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Cyrille THOMAS

SCHILTIGHEIM

Electionsmunicipales 2026

RETROUVEZ GRATUITEMENTRésultat municipales à Chaville
Résultat municipales dans les Hauts-de-Seine

En résumé

Mes compétences :
Arm
ASIC
ChIP
Design
DFT
FPGA
Leader
Physical design
Soc
STA
SYnopsys
System On Chip
Team Leader
Test
Verilog
VHDL
VLSI

Entreprises

  • Bull SAS - ASIC Physical Design Team Leader

    SCHILTIGHEIM 2010 - maintenant Responsible for physical design team in 40nm and 28nm ASIC projects.

    Missions of the team include front-end part (synthesis, Design For Test, timing constraints and static timing analysis) and back-end part (physical implementation, from RTL to GDS2) for multi million transistors integrated circuits.

  • Bull SAS

    SCHILTIGHEIM 2008 - 2010

  • Bull SAS - ASIC Physical Design Engineer

    SCHILTIGHEIM 2008 - 2010 Physical implementation of two sub-blocks within a 250 million transistors in 90nm, from RTL to GDS2: floorplanning, standard cells placement, clock tree synthesis, signals routing, static timing analysis (STA).

    Supervision for physical designers in charge of remaining sub-blocks.

  • Bull SAS - ASIC Front-End Engineer

    SCHILTIGHEIM 2006 - 2008 Responsible for Design For Test specifications and implementation for a 250 million transistors integrated circuit.

    Use of DFT Compiler and DFT Max Synopsys tools for scan chains insertion (normal and compression modes). Logic and memory BIST integration/implementation.

  • Bull SAS - ASIC Logical Design / Integration Engineer

    SCHILTIGHEIM 2005 - 2006 Taking part in architectural choices for a 90nm ASIC in 90nm, managing memory coherency for servers based on Intel processors.

    Responsible for logical design of the physical layer of the chip, in close collaboration with Avago Technology foundry (formerly Agilent) for integration of specified-by-Intel IPs (Quick Path Interface) and very high speed SerDes (8Gb/s).

  • Bull SAS - ASIC Logical Design Engineer

    SCHILTIGHEIM 2004 - 2005 Co-responsible for logical design and synthesis of an ASIC part in 180nm technology.

    Co-responsible for chip timing constraints definition and application with IBM Static Timing Analysis tools.

  • GenNum Corp. Canada - Engineering internship

    2002 - 2002 Integration and Prototyping team member, working on the design of a Firewire --> Ethernet protocols converter. Validation of VHDL units with System On Chip development platform (ARM-FPGA).

  • Bull SAS - FPGA Verification & Design Engineer

    SCHILTIGHEIM 2002 - 2004 First, development in Verilog of exciting/replying blocks for validation in global verification environment.

    Then, design of a block on Xilinx FPGA target.

Formations

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