Olivier GIARD

En résumé

Entreprises

• NXP - Analog designer, Project leader

  2007 - 2012 Main scope:
  Development of high speed ADC ICs
  
  -- Development and deployment of common UNIX shell for all projects over DesSync environment.
  This environment make all designers to works on all projects through a single input point interface.
  All projects environment and customization are centralized. This simplify the administration of libraries update and environment setting in each user unix account.
  
  -- Design of dis-overlap function for ADC
  Study of PSRR on ECL and CMOS transmission gate.
  Design of programmable delay non-overlap clock.
  optimization of design parameters with Adapt software (NXP optimizer).
  Sizing of clock tree in the ADC IC for correct phase alignment
  
  -- Design of current programmable LVDS output buffer @ 250MHz
  
  -- Project leader of 16 bit low power ADC
  I participate in the development of the design, manage planning and tracking of all tasks.
  Coordination of design and layout of all blocks in the IC.
  Multi-site project leading (Eindhoven-NL, Caen-Fr)
  
  -- Knowledge development:
  - Development of automatic placement software for IC PAD ring building.
  - Various utilities in Cadence skill for design flow improvement
  - DesSync/Centralized vault management
  - ADC knowledge

• IDT - Senior analog designer

  2007 - maintenant - Leading of 12Gbps JESD204B (derived from CEI-11G-SR) TX SerDes IP in TSMC CMOS 65nm.
  - Desing of Low jitter 2GHz clock buffer and clock distribution design for 500Msps ADC.

• NXP - RF design flow engineer

  2005 - 2007 Development of flow for RF design.
  
  -- Automatic testing of deisgn Kit extraction flow.
  I did develop a flow for testing layout extracted devices to guaranty
  the correct design kit extraction rules.
  
  -- Benchmarking of ADS simulation software.
  I develop several test bench for analyzing ADS simulator and its performances versus Spectre.
  
  -- Development of automatic test bench for simulation.
  Based on my needs of numerous number of simulation for Monte-Carlo analysis, I did develop a flow and software for creating simulation test (Monte-Carlo, sweep and corner) by using several Spectre process in parallel to reduce design characterization. The flow is based on LSF system.
  This flow was used in the process analysis of wireless product Zelda to find process dependencies of all specifications of the IC.
  The flow was integrated in a CAD product in NXP for all designer.
  
  -- Development of process block and software for mismatch analysis.
  This development was based on the lack of correct software able to help designers to find root cause of matching problems.
  This flow is based on Monte-Carlo and correlation analysis.
  A special Matlab program has been developed in Matlab to retrieve
  devices that contribute on mismatch deviation during simulation.
  The software analyses the correlation between mismatch parameters and measurement from Monte-Carlo results. This flow has been implemented in Spectre and Cadence after a collaboration with Cadence R&D.
  
  -- Deployment of Robust IC design on NXP
  I did present over the design community all methodologies and flow to improvement IC yield during design phase.
  I did participate on task-force to promote and improve the yield of design.
  
  -- Knowledge development:
  - skill programming
  - ksh, awk, sed, tcl programming
  - Cadence dfII environment
  - ADS sim, ADS Ptolemy and RFDE software
  - Monte-Carlo analysis improvement
  - Co-simulation Spectre/NCsim, ADS/NCsim

• Philips Semiconductors - RF IC Design leader

  Suresnes 2001 - 2005 Main scope:
  Design leader of RF receiver for satellite (DVBS) (productsTDA8260 TDA8261 TDA8262
  
  -- STV2160 IC Debug and industrialization.
  I did participate to finalize the STV2160 (ZIF DVB-S receiver) generation IC.
  Debugging of the PLL of the IC. I did apply knowledge previously developed in STM in noise analysis of PLL to solve problem of phase noise in STV2160.
  
  -- Project leading of STV2165 IC.
  This IC was a Multi Chip module (MCM) of the fronted analog receiver (HS5) with digital channel decoder IC (CMOS18).
  The project did stopped at tape-out for strategic reasons.
  
  -- Project leading of STV2161/2 IC.
  This IC was an upgrade of the STV2160 with full integrated LNA and 0.8 to 2GHz PLL in Qubic3
  A high importance was made on the Monte-Carlo analysis and high level of testability for industrial testing.
  The IC did change of Fab (US to NL) without any modifications of industrial test program, and without modification of yield (higher than 95% at wafer test)
  I did made the complete top level layout of this IC
  
  -- TDA18211, Zero IF DVB-T receiver development
  This IC is a MCM with Qubic4+ die and CMS devices on laminate substrate.
  I did develop a Matlab software to investigate the budget in noise, linearity and bandwidth of each bock of the signal path.
  
  -- Patents:
  - automatic test for BF and RF counters for industrial test cost down.
  - Improvement of AGC RF loop control by the channel decoder.
  - automatic calibration of VCO in double loop PLL system.
  
  -- Knowledge development:
  - Wide band PLL (0.8 to 2GHz) with double loop for jitter improvement
  - improvement on noise behavioral of PLL
  - RF budget analysis and block specification for RF design
  - Zero IF, double-conversion system
  - IC testability for industrial testing
  - Monte-Carlo yield analysis and layout matching improvement
  - Matlab software development for noise and RF budget model including GUI development.
  - Risk analysis on project
  - Layout design flow improvement

• ST microelectronics - Analog IC designer

  1998 - 2001 Phase noise analysis of GSM IC PLL. Simulation of phase noise with ELDO and Spectre
  
  Development of an architecture of PLL with fast locking phase in technology BicMOS6G.
  The basic idea of this architecture is simple. During locking phase, the PLL run in fractional mode
  and then the PLL pass into integer mode in normal mode when lock is done.
  The implementation is quite simple and does need only few digital gates.
  
  Knowledge development:
  - PLL high frequency (2.3GHz)
  - fractional PLL
  - phase noise in PLL: analysis of noise in each part of the PLL.
  Simulation of total output noise with MathCAD software.
  
  Training:
  - one week on PLL with Bar-Giora Goldberg in Catania.

• TCEC - Analog designer, IC architecte, Design leader for analog TV at TCEC (THOMSON-ST Join venture)

  1993 - 1998 This first experience started with learning of 50Hz ICs STV2160/1 (50Hz) beam control analog processor. Analysis of yield production
  
  As a project leader of the new generation of the STV216X, I start development of product STV2162 (30mm² in HF3CMOS).
  I introduce new architecture with several digital implementations and new concepts in the IC.
  
  I did start the pre-study of next generation of scanning ICs for all type of CRT TV (Home, PC, VGA, Proscan,...) and for all type of frequencies.
  Because of high risk of CRT destruction due to fast change of beam frequency, an architecture was invented to control frequency changes.
  Unfortunately, first flat screen appears on the market. Thus , the development of analog CRT TV ICs was stopped in TCEC.
  
  -- Patents:
  - improvement of jitter in horizontal synchronization system.
  - speed improvement of industrial test during TV assembly in production line by creating auto-test pattern on IC
  - writing of various patents for improvement and simplification of technics to remove TV geometrical default on picture.
  
  -- Knowledge development:
  - PLL low frequencies ( 1 to 27 MHz)
  - ring oscillators
  - digital design: divider, up/down counter, preload counter, I2C bus...
  - verilog: development of digital library for I2L logic in Verilog
  - yield analysis
  - simulation analog (ELDO), analog/digital (ELDO/Verilog)
  - Monte-Carlo: development of models code to simulate yields
  - lab manipulation, micro-probing
  - Xlinx programmings
  - layout: analog cells, top assembly of ICs, Check with Diva and Dracula
  - project leading
  
  -- Trainings:
  - analog design (Grenoble, EPFL Lausanne,...)
  - Cadence analog simulation
  - digital design: cadence training on verilog
  - project management, risk analysis

Formations

• ISAE SUPAERO

  Toulouse 2015 - maintenant Advanced Master

• ENSERB

  Talence 1989 - 1992 Graduate of Ecole Nationale Supérieure d'Electronique et de Radioélectricité de Bordeaux

• Université Bordeaux 1 Sciences Et Technologies ENSEIRB

  Talence 1989 - 1992 micro-electronics

Réseau

• Arnaud BIALLAIS

• Eric MAURICE

• Hervé DÉCHAUFOUR

• Jean-Francois AUPEE

• Jean-Marie RETROUVEY

• Jérôme LANGANAY

• Laurent LANGLAIS

• Sophie GIARD

• Stéphane JOUIN