Mes compétences :
Chemistry
Chimie
Process
Process engineer
Scientific
Semiconducteurs
Semiconductors
Entreprises
STMicroelectronics
- Process Expert - Surface preparation / Wet
2012 - maintenantstrong expertise (15 years) in surface preparation, materials and process characterization
all kind of batch and single wafer cleaning tools.
The Expert role enables me to :
* be a problem solver for mature, high yielding technologies
* bring high value for new process definition
* demonstrate high innovation skills (2006 golden patent award)
* deliver engineers technical coaching & knowledge cross fertilization
* define long term roadmap in my area
* grow a wide worldwide professionnal network from universities, suppliers, labs, IC manufacturers
42 publications in international conferences
strong process integration knowledge in:
CMOS (from 120 down to 14nm), BiCMOS, SOI, FDSOI, CMOS Image sensors, embedded DRAM & non volatile / flash memories, Photonics from technology start up to high yielding devices.
Advanced surface treatments course given at UJF (University Joseph Fourrier Grenoble)
Management of several PhD studies:
- photoresist adhesion loss during wet etching
- wet etchant permeation through photoresist
- nanoparticles spray cleaning on hydrophobic surfaces (ongoing)
2014:
* invited at UCPSS conference, Brussels
* CMOS Image sensors: innovative process development => +10 millions $ savings
2010 - 2012Technical management of 6 process engineers in Wet.
Technology transfer of CMOS 32/28 nm Low Power nodes.
28nm FDSOI node development
embedded DRAM & Flash memories development
IBM
- Surface preparation R&D Senior process engineer - on IBM East Fishkill, NY, USA
Bois-Colombes 2008 - 2010Click to edit position descriptioncollaboration within IBM Alliance to develop High K Metal Gate technology.
latest node (32 / 28 / 20nm)
NXP (Philips) semiconductors
- Team Leader Process FEOL
Team Leader / R&D Process Engineer (3 years)
- world premiere: development + industrialization of pre gate oxide cleans on “single wafer” tools
+ 4% yield increase i.e. +10 millions $ annual income gain
- Responsible of Surface Preparation development for CMOS 65nm, 45nm, SOI & embedded Flash 90nm
Production Sustaining (1 year) :
- Start-up of the 300 mm plant at Crolles(France) (3 billions $)
- development & follow-up of CMOS 120 & 90 nm technologies
- Industrialisation of « single wafer » FEOL cleaning equipments
Process Engineer surface preparation : (1.5 years)
Pilote line 300mm at Meylan(France) / French Telecom R&D cleanroom
- Responsible of FEOL surface preparation process
- World Premiere : 1st FEOL single wafer cleaning equipment
- Productivity (cycle time) & quality (defectivity reduction)
Nantes2000 - 2001EUROFINS SCIENTIFIC (leader in Europe & USA)
Foodstuffs / pesticides / bio analyses Lab
Development of analyses methods. Quality & Safety enhancement. Staff training.Interface between firm’s salesmen, french technical experts & german lab.
