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Prasanth PUSHPARASAH

Meudon

En résumé

Open to any opportunity close to Paris. Working as electronic engineer for more than 14 years in embedded memory compilers developments. Having a deep knowledge in circuit and layout designs in many CMOS technologies, 130nm to 14nm FinFets. Expertise in reliability topics like electro-migration and IR-Drop studies, FinFet self-heating and aging studies. In charge of memory compilers development methodologies and flows for more than 4 years, leaded and managed many working groups and people.

Mes compétences :
Calibre
Communications
Layout
Microélectronique
Mobile
Virtuoso
Rational ClearCase
Perl Programming
PC Hardware
Project planning
Circuit Design
Cadence Software
memory development
full custom mask development
flow implementation
XA
Team Management
Tcl/Tk
SKILL programming
Quality Assurance
OneNote
Microsoft Word
Microsoft Visio
Microsoft SharePoint
Microsoft PowerPoint
Microsoft Office
Microsoft Excel
Memory Design
JIRA
IC Design
HSPICE
Foundry
Flow training
Feature Films
Development coordination
C++
C Programming Language

Entreprises

  • Intel - Methodology Team Leader

    Meudon 2013 - maintenant * Project planning, resource allocation and priority definition. ;
    * Methodology definition and flow implementation:
    * Mismatch Flow: circuit statistical studies based on MPP/MPP2 algorithms. ;
    * Characterization Flow: spice simulations based on compiler architectures critical paths to generate timing and power data's. ;
    * Back-End QA Flow: memory generations based on PERL programming codes and QA (DRC, LVC, ERC etc ...). ;
    * Functional Validation Flow: functional validation based on spice test vectors and fast-spice simulations.

    * Reliability Flow: spice simulations based on generated memories to optimized physical routing. ;
    * FullCut Flow: spice simulations based generated memories to correlate characterized timings and powers. ;
    * Data-management Methodology: defined way to use ClearCase API's (config specs, labels, branchs). ;
    * Release Methodology: defined methodology for deliveries between development team and QA team. ;
    * Memory Generator: data-structure definition for PERL codes to generate physical and netlist memories based on developed leaf-cells. ;
    * Physical Wrapper to ease memories integrations into SoC for Intel's FinFet nodes, and reduce development time. ;
    * PDK integration in memory projects.
    * Flow supports for memory designers.
    * Flow training's for users.
  • Intel - IC Circuit Designer

    Meudon 2011 - 2013 * Statistical studies (MPP/MPP2 Algorithms) for bit-cells (RAM, ROM and RF), Sense Amplifier, Timer (dffc) and TVC (Transient Voltage Collapse) circuits.
    * Critical-path implementations (RAM and ROM). ;
    * Timing and Power characterization (RAM and ROM).
  • Infineon Technologies - IC Mask Designer

    GEMENOS 2003 - 2011 * Floorplanning and Full Custom Layouts for embedded memories and e-fuses (SPSRAM, DPSRAM, ROM, EFUSE)
    * Advanced knowledge in MOS technologies : 130nm, 90nm, 65nm, 40nm, 28nm
    * PERL based Memory Generators Development (Physical and Netlist)
    * Back-end Qualifications (DRC, LVS, ERC, AntenaDRC, etc ..)
    * Electro-migration and IR drop studies ;
    * SKILL programming ( Cadence programming language) ;
    * Memory Compiler releases and supports for EDA View generations
  • Disneyland Resort Paris - Part Time Waiter

    Chessy 2000 - 2003 * Part Time Waiter (Week-End and School Vacations)

Formations

  • ESIEE Paris

    Noisy Le Grand 2000 - 2004 Technologue

    ESTE (Groupe ESIEE)
    section ESTE Microelectronic.
    Last year done as apprentice.

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