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Tarik SAFAA

GRENOBLE

En résumé

• SoC Low Power Verification
• SoC communication network protocols: APB, AHB
• SoC RTL performance measurement / analysis / methodology
• Embedded software
• Processor: ARM , Motorola
• Programming Language: ASM, C, C++, Perl, shell
• HDL: VHDL / Verilog / SystemC
• Hardware Verification Language(HVL): PSL / e language
• Run tests on the RTL and debug it using software-hardware co-simulation environment, full RTL or Gate environment, work in NCSIM and QUESTA environment
• Find and identify hardware bug and plan solutions with spec/design owners
• Development of Engineering Patterns for validation team
• Debugged different IP’s : SBAG, ICN ,SMBUS, HSI2C, CRYP, SCR, GPIO, MEMORY , HSI , SPI , RT

Mes compétences :
Gestion de projet
Electronique
Linux

Entreprises

  • St ericsson - Soc verifivation engineer

    GRENOBLE maintenant

  • St Ericsson - Soc Verification Engineer

    GRENOBLE 2009 - maintenant • SoC verification for Mobile Platforms : Application Processor
    • SoC Low Power Verification
    • SoC communication network protocols: APB, AHB, AXI
    • Embedded software
    • Processor: ARM , Motorola
    • Programming Language: ASM, C, C++, Perl, shell
    • HDL: VHDL / Verilog / SystemC
    • Hardware Verification Language(HVL): PSL
    • Run tests on the RTL and debug it using software-hardware simulation environment, full RTL or Gate environment, work in NCSIM and QUESTA environment
    • Find and identify hardware bug and plan solutions with spec/design owners
    • Development of Engineering Patterns for validation team
    • Debugged different IP’s : SBAG, ICN ,SMBUS, HSI2C, CRYP, SCR, GPIO, MEMORY , HSI SPI , RTT,UART……

  • St Microelectronics - Analog Designer

    2006 - 2009
    • Design of a LDO for power management application in cmos 32nm technology
    • Design Analog Blocks for MIPI (High Speed Links) application: delays, Test Samples clock, Biasing, LP transmitter, Impedance calibration Block. Predriver Block
    • Design of DAC 24bits with Differential output current For Audio Application Development of Analog parts f The IP :Band Gap , OPA,OTA, current sources , Voltage regulators
    • Studying and analyzing existing architecture , comparing different architecture in different technologies , researching for new design solutions
    • Validation of the IP by doing schematic Simulation (CADENCE , SPECTRE ) and Post layout Simulation (CALIBRE, ELDO)
    • Preparing design documentation and updating the design specification
    • Working in collaboration with laboratory measurement engineer on the characterization of the chips.

  • Infineon Technologies - Product Engineer

    GEMENOS 2005 - 2006 • Evaluation of a Relay Driver with Embedded MCU & LIN transceiver for a window lift application designed in BiCDMOS technology.
    • Studying and analyzing the functionality of the SBC
    • Learning about SPT (Smart power technology)devices and technology
    • Learning about the fundamentals of Smart power Ics and circuit design
    • Simulation of the integrated circuit (CADENCE : analog , mixed signal and statistical simulations)
    • Calibration the measurement interface
    • C programming software for MCM (Multi- Chip-Module) tests.
    • Configuration of samples for the customer

Formations

Réseau

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