-
Thales Communications & Security
- Senior Asic Designer
Colombes
2016 - maintenant
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SCALEO CHIP
- DFT engineer
2011 - 2016
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Texas Instrument
- Verification engineer
Colombes
2010 - 2011
Verification lead of security on omap5 devices
-verification and test plan creation
-testcase development
-debug of security feature
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Texas Instrument
- Design For Test Lead
Colombes
2004 - 2010
DFT Lead for the following projects (OMAP1710, OMAPV1230, OMAPV1035, Attila Platform)
-) Interact with cross-functional teams, customers and program management to drive closure of open items and report DFT team progress
-) Ensure good DFT and testability to meet cost, quality and reusability goals
-) Insure Stacked-Die DFT, Burn-In and other activations are defined in a early phase
-) Drive and coordinate DFT team design activities (design, RTL and GLS validation, test pattern generation).
-) Ensure DFT is validated before Tape / PG and test patterns are available before silicon out.
-) Support for Customer Returns
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Altran
- DFT engineer
Vélizy-Villacoublay
2002 - 2003
Altran consultant working for Texas Instrument as DFT engineer for Texas Instruments on OMAP 1610
-) Responsible of DFT top level testbench
-) Generation and debug of functional test pattern with Product Engineering team
-) Support for OMAP 161x projects
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Altran Europe
- Design Engineer
Vélizy-Villacoublay
2000 - 2002
Altran europe consultant working as designer for Alcatel-Bell (Antwerp) on VDSL chipset.
-) Module VHDL design
-) RTL modules validation
-) Top level validation
