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Robert Bosch Gmbh
- Semiconductor Technology & IP Management
Saint Ouen Cedex
2015 - maintenant
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ST Microelectronics
- Semiconductor Technology Management & Senior Member of Technical Staff
2012 - 2015
Within the Imaging division, in charge of driving the advanced digital technology node developments to fit ISP product needs.
* Providing product feedback to process development team for process optimization ;
* Ensuring on time technology deliveries for Imaging product development and ramp-up ;
* Supporting sales and marketing teams by running foundry competitive benchmarks and promoting our technology in customer meetings. ;
* Support Imaging project team (design, validation, engineering) for all topics related to process or design platform from architecture specification (performance/power estimation) to product tape-out and engineering characterization.
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ST-Ericsson
- Semiconductor Technology Management & Member of Technical Staff
2009 - 2012
Semiconductor Technology Management - Member of Technical Staff
Member of Technical Staff in charge of the identification of semiconductor technologies, foundation IPs and design platform to create a competitive advantage for tablets and smartphone platforms. This includes running competitive intelligence and benchmarking, driving technology selection, defining the detailed requirements of ST-Ericsson foundation IPs and design platforms and driving their execution with external providers aligned with product roadmap.
Main foundry interface for a multi-site mixed-signal product development.
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NXP Semiconductors
- Technology, Design & Flows - Consulting Principal & Design Engineer
Colombelles
2007 - 2009
Acting as an internal consultant bringing transistor level design expertise within various Business Units development groups from mobile applications to automotive and identification. Expertise is covering specific memory developments, (ultra dense ROM for Identification), hard IP customizations for new technology requirements (deep Nwell usage, DFM awareness), program management and foundry partner interface.
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NXP Semiconductors
- Advanced Memory Design R&D Manager
Colombelles
2006 - 2007
Crolles2 Alliance - Advanced Memory Design R&D Manager
Technical leadership of a multi-cultural team of expert memory designers from the three parent companies of the Crolles2 Alliance. Studies were targetting new embedded memory concepts for 45nm/32nm CMOS technologies (original design solutions for SRAM, Z-RAM on bulk, 3T DRAM). Communication with parent companies at different hierarchical levels was a key aspect:
* Organization of workshops to define group objectives with parent companies program managers.
* Deployment and support of results to parent companies development groups
* Close interaction with foundry development for exploration of new technologies and designs.
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Philips Semiconductors
- Process and Library Technology - Advanced Memory Group Leader
Suresnes
2002 - 2006
Technical leadership of the Advanced Memory group. Group activities were oriented towards specific embedded memory generator developments in advanced CMOS technologies (e-fuse, OTP, MRAM, eDRAM, SRAM, ROM, in 90nm and 65nm) and with customer specific IP integrations on state-of-the-art SoC (LCD optimized SRAM cuts, custom RTL BISTAR engine, ECC RTL module generator, MRAM memory controller and BIST).
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Avant! Corporation
- Library Development Group Manager
1997 - 2002
Responsible for the development of a complete library product line (PDKs, S.C., memory compilers, standard IOs) in 0.18m and 0.13m technologies (including close interaction with the targeted foundries - TSMC, Chartered and UMC). Coordination of the work of design engineers from 3 different sites (Sophia, Shanghai and Moscow).
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Compass Design Automation
- Customer Library Services Manager
1995 - 1997
In charge of a team of 5 engineers in France and the coordination of the work of a team of 10 engineers in Russia. Custom products developed in the group were ranging from simple standard cell libraries to more complex compilers (datapath, memories) or even analog cells in sub-micron CMOS processes. Responsibilities included definition of the SOW (Statement Of Work), design reviews with customer, final delivery and application support.
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Compass Design Automation
- Advanced Library Group Project Leader & Project leader
1991 - 1995
Compass Design Automation Sophia Antipolis - Project leader for sub-micron process projects both in design and CAD, in the following areas:
* PDK (process design kits) developments for sub-micron technologies: follow up of process integration and foundry Endorsement in the Compass CAD flow, tight interface with main foundries (TSMC, Chartered, UMC, Tower).
* CAD development: Implementation of a new timing simulation model in a library evaluation tool. ;
* sub-micron design: architecture definition of a new symbolic high density standard cell library - design of a generic testchip including all the different symbolic libraries and compilers - full-custom design of customers specific functionality (SOI S.C., low voltage crystal oscillator...). ;
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VLSI Technology
- Library Development Design Engineer
Buc
1989 - 1991
Development of full custom standard cells, gate array and datapath compiler libraries in CMOS.
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Fairchild Semiconductor
- Research Engineer
San Jose
1985 - 1986
Design of SSI, MSI and LSI integrated circuits in CMOS 2um for the "FACT" family.
