Menu

Johan BOURGEAT

GRENOBLE

En résumé

Customer specifications analysis vs ESD standard:
- Analysis of customer needs
- Propose adapted solution
- Studied new ESD protection conception
- Anticipate Risk (Latch-up)

New Conception
- Semiconductor Physics (Bipolar, MOS, SCR, Diode)
- Good knowledge of Microelectronic process
- Propose new dedicated Simulation Setup
- Conception of devices on silicon (DOE)
- Anticipate new measuring procedure (Test of device)

Simulation tools:
- Sentaurus: TCAD (semiconductor equation)
- Cadence: Eldo (model simulation)
- Agilent: ADS/Momentum (Maxwell equation)
- Apache: Redhawk (Metal resistance extraction)

Design tools: Test vehicle/DOE for DC/ESD/RF
- Cadence: Virtuoso/icfb
- Maxwell: LE (Training)

Measurement and Debug Analysis:
- DC/ESD/Noise Electrical Bench characterization
- Good knowledge on Failure Analysis and tests for
Phenomenon reproduction

Report:
- Data treatment on Excel
- Report on Power Point/Word

Other Competences:
- Trainer and referring
- Patent (14)
- Publication (23)

Social:
- Adaptability / Flexibility
- Fast learning / Team spirit
- Collaboration with different Teams

OS:
- Windows / Linux New Conception: (R&D Devices)

Mes compétences :
Microelectronics
Gestion de projet
Fiabilité produit
R&D solution Client

Entreprises

  • STMicroelectronics - ESD/EOS/LU/Reliability Expert

    2011 - maintenant Development of specific ESD Solution, for CMOS and BiCMOS technologies and deployment of the solution inside ST products:
    - ESD power devices referee for the team and external customers
    - R&D on New power device and trigger circuit development for a spread of applications : (Low leakage, Low capacitance, RF up to 100GHz, High Voltage, high Energy)
    - Patents submission before sharing the solution
    Study and development of low capacitance solutions (>20fF) for high speed RF application for setup box or Space applications in advanced technology node:
    - Set dedicated Simulation Flow to validate the concept
    - Propose specific Measurement setup
    Development of high energy protection (30A) to integrate electronic board components inside the integrated circuit (IC) to reduce the final product cost and deployment in further technology nodes.
    Secure the customer product by Reviewing the ESD strategies, Debugging and Analysing the customer complain in short time frame to avoid production shutdown.

  • STMicroelectronics - PhD Student

    2007 - 2010 Study, Simulation, Development, Measurement, Analysis, Patent and Publication of advance new device in deep technology node:
    - Research activities between two institutes collaboration
    - International scientific presentation

  • STMicroelectronics - Training

    2006 - 2006 Project: Study on reliability and Low Frequency noise (LF) of bipolar transistors under reverse, forward and mixed-mode electrical stresses

    Objective: Study about base current degradation after different electrical constraints and 1/f noise degradation in transistor bipolar base

  • CEA - Training

    PARIS 2005 - 2005 Project: Study on gold colloidal distribution on the silicon substrate to grow silicon nanowires
    Mean: Used CVD (Chemical Vapor Deposition) for wire growth, SEM (Scanning Electronic Microscope) and STM (Scanning Tunneling Microscope) for characterization

Formations

  • Université Toulouse 3 Paul Sabatier

    Toulouse 2007 - 2010 PhD Student: Study of ESD Protection for Advance CMOS Technology Nodes (CMOS032nm), Collaboration between CNRS LAAS, GEET UPS Université de Toulouse and STMicroelectronics Crolles

  • Université Grenoble 1 Joseph Fourier

    Saint Martin D'Hères 2002 - 2006 MASTER Research Micro and Nano Electronics, Components and Materials Physics specialty - UJF Grenoble, fifth level certification equivalent

Réseau

Annuaire des membres :