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William NATTER

Toronto

En résumé

- Revues de specifications de FPGA
- Developpement de plans de simulation et tests en laboratoire
- Simulation de gros FPGAs (Xilinx, Altera) utilisant Questa / NC-Verilog
- Developpement de scripts et programmes en Perl, Tcl, Expect, Bourne Shell, Verilog et SystemVerilog
- Tests de FPGAs en laboratoire

Mes compétences :
Altera
ASIC
Cadence
Conception
DSP
FPGA
Hardware
HARDWARE & SOFTWARE
MENTOR
ModelSim
Nortel
Perl
Scripting
SCRIPTS
Shell
Simulation
STA
SYnopsys
TCL
traitement de signal
Verilog
VHDL
Xilinx

Entreprises

  • Nortel - Component Engineer

    Toronto 2008 - 2008 Supplier approval and part qualification
    - Verified the capability of new suppliers to produce reliable, quality parts (was slated to audit suppliers in 2009)
    - Requested and checked proofs that parts met reliability requirements
    - Provided feedback on supplier capability in cost reduction initiatives
    - Participated in requirements specification re-definition/re-write
    - Gathered crucial information for linear price projection initiative

  • Sandvine Corporation - Senior Software Engineer

    2008 - maintenant - Firmware: integration of a new bypass blade
    - Manufacturing:
    * software testing of locally manufactured, complex electronic products
    * responsible for validating new product to be sent to beta testing site

  • Nortel - FPGA Verification Engineer

    Toronto 2007 - 2008 FPGA verification through simulation and lab testing
    - Improved testbench maintainability, consistency and ease-of-use while keeping deadlines
    - Minimized coding errors and increased test coverage of lab test scripts
    - Sped up in-card testing by making lab test scripts self-checking and remotely runnable
    - Created and supported Bus Functional Model for a new DDR-based proprietary protocol

  • Nortel - Basestation System Designer

    Toronto 2006 - 2007 Lab testing, integration, and product integrity testing
    - Tested latest generation wireless equipment in lab for conference demonstration
    - Tested product integrity of advanced wireless equipment
    - Shortened climate chamber use for safety testing by automating card boot-up

  • Nortel - Timing Verification Support Engineer

    Toronto 2000 - 2006 Timing & power analysis tool support and methodology development
    - Achieved 0-timing-defect in 3 internal ASIC static timing analysis contracts
    - Debugged and fixed internal customers’ timing analysis scripts
    - Created and sped up internal timing analysis audit tool
    - Improved ease of use and thoroughness of internal timing analysis methodology
    - Taught methodology to internal customers
    - Created first timing bottleneck analysis tool, before First Encounter’s
    - Increased internal customer satisfaction by visiting while on vacation
    - Received 2 customer appreciation awards for contracts started just weeks after being hired

Formations

Réseau

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