Saint-Ouen Cedex

En résumé

Responsible for the overall development of complex and high quality integrated circuits from specification to production. This role includes managing projects with teams located on different countries for a more efficient execution in terms of schedule, quality and cost, resolving technical challenges (several power/voltage domains, multiple clocks domains…) and ensuring best IP, SOC, EDA, product engineering, and technology team collaborations.

Mes compétences :
Chef de projet
Téléphonie mobile


  • Samsung Electronics - Senior Program Manager

    Saint-Ouen Cedex 2013 - maintenant Responsible for the supervision of complex and high quality integrated circuits’ development from specification to production. This role includes managing large scale programs in multi functional areas in order to greatly exceed performance and delivery expectations.
  • TEXAS INSTRUMENTS - OMAP543x Design Manager

    Villeneuve-Loubet 2009 - 2013 OMAP5430 and OMAP5432 chips arefully functional and currently in the initial phase of production. I am responsible for the OMAP543x project development by

    - Defining project scope and support product definition based on different analyses (cost estimation, “What if” scenarios, risk managements …)

    - Evaluating resource needs, project schedule, task definitions & assignments…

    - Specifying bug tracking system requirements to match the project development needs and accurate matrics allowing the correct checkers the execution

    - Evaluating decisions based on risk analysis between schedule, quality and cost needs.

    - Driving the development of OMAP5 IC from RTL to GDSII. This IC is development in 3 different locations (India, US and France) and putting in place alternative plans to allow concurrent engineering between IP & TOP level teams and review development plans for better schedule optimization.

    - Delivering the project on time with the right quality and cost.

    - Based on quality criteria’s reviewed via metrics (bug curves, timing violation status…), put in place corrective actions & contingency plans for better schedule optimization.

    - Debugging TI process during pre/post Silicon Out (OMAP5430 is TI’s first product in 28nm) and Working with library and product engineering teams to solve modeling issues found during Silicon Validation.

    - Preparing, providing answers and passing internal and external ISO audits (ISO 9001 certification)

    - Leading the design team for allowing debug help during prototype validation and also for improving the process used by lessons learned for following projects
  • Texas Instruments - SOC Design Leader

    Villeneuve-Loubet 2005 - 2009 Lead the IC development on several OMAPx products and 2G, 2.5G and 3G Modem by:

    - Driving the design team (up 35 people based in France & Serbia) from specification to production: RTL integration, DFT, Synthesis, STA, Place & Route, Physical Design (GDSII creation) Power optimization, Database management with EDA & IT team supports…

    - Evaluating & Solving technical challenges on low power (4 voltage & 15 power domains), clock performances (14 DPLLs; 50+ clock domains; frequency up to 2Ghz) and IP functionalities (ARM A9/A15, EDGE/UMTS/DigRF, DDR3, LPDDR2, USB3, Graphic &Video Accelerators, Display & Camera sub-systems…)

    - Supporting on their own sites the IP development teams based in United-States, India, Japan, France by defining release quality and contents to SOC level team and putting in place alternative plans to allow best concurrent engineering between IP & SOC teams.

    - Reporting regular status to management and costumers based on the accurate metrics.

    - Providing first level support to costumers based on their debug and board developments
  • Texas Instruments - Timing Closure Lead

    Villeneuve-Loubet 2003 - 2004 Responsible for Static Timing Analysis and the timing closure phase of 2 OMAP ICs (OMAP1610 and OMAP1710)
    Leader of a team of 4 people
  • TranSwitch Corporation - System on Chip Designer (spec, coding, verification)

    2001 - 2002 In shelton Connecticut (USA), I Worked on :
    - Ensuring best in class quality of Ethernet / SONET chips (130nm) by Formal verification (Vera)
    - Ensuring best in class quality of ATM chips (Posphy & Ethernet devices) by Design verification
    - Specifying, designing and verifying a “mailbox” IP for Motorola, Intel microprocessors.
  • TranSwitch Corporation - IC Design &Verification Engineer

    1999 - 2000 In Lausanne (Switzerland), I worked on
    - Verifying a QT1Framer and DS0/DS1 cross connect chip by using C++ & modelsim (API).
    - Specifying, designing and verifying IPs using Posphy, Utopia transfert protocols.