MARTIGUES
* Aptitudes Techniques:
- Etude d'architectures Low Power (Triple-well)
- Design de contre-mesures pour circuits intégrés sécuritaires CMOS
- Injection de fautes (Laser)
- Conception de circuits analogiques (Design analog)
- Power Managment (bandgap, LDO)
- Layout
- Radio fréquence, RFID
- Traitement du signal
* Formations :
- Doctorat CIFRE à STMicroelectronics - Modélisation d’injection de fautes Laser et design sécuritaire de contre-mesures sur architecture Low Power.
- EF international School: école de formation d'anglais (9 mois) à Vancouver (Canada).
- Master MINELEC recherche, spécialité: conception de circuits intégrés.
- Ingénieur ISEN (Électronique, Microélectronique, Télécommunication, Etude du signal, Automatique, Algorithmique, Réseau).
* Compétences techniques:
- Cadence: Virtuoso, Analog Artist, Layout XL
- Mentor Graphics: Eldo, Calibre
- Techno STMicroelectronics CMOS 90nm,65nm, 40nm
- Système d’exploitation UNIX
- Langage : C, VHDL, PEARL
* 10 Publications & Conferences IEEE + 2 Brevets:
- ISTFA 2014: "Characterization and Simulation of a Body Biased Structure in Triple-Well Technology Under Pulsed Photoelectric Laser Stimulation"
- IRPS 2015:"Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation"
- IPFA 2015:"Electrical model of a PMOS body biased structure in triple-well technology under pulsed photoelectric laser stimulation"
- IOLTS 2015:"Laser fault injection into SRAM cells: Picosecond versus Nanosecond pulses"
- IOLTS 2015:"Experimental validation of a Bulk Built-In Current Sensot in Detecting Laser-Induced Currents of an hybrid well-taps target"
- ESREF 2015 & Journal Microelectronics Reliability:"Electrical model of an Inverter body biased structure in triple-well technology under pulsed photoelectric laser stimulation"
- DFTS 2015:"Influence of triple-well technology on laser fault injection and laser sensor efficiency"
- DFTS 2015:"Electrical modeling of a picosecond pulsed photoelectric laser stimulation of a D Flip-Flop in 40 nm technology"
- PATMOS 2015:"Dynamic Current Reduction of CMOS Digital Circuits through Design and Process Optimizations"
- RADECS 2016:"Laser testing of a double-access BBICS architecture with improved SEE detection capabilities"
* Spécialités:
Analog Design
Security (Laser Fault injection and countermeasures design)
Power Managment
RFID
CMOS 40nm 65nm 90nm
Mes compétences :
Microélectronique
Sécurité
Electronique
CMOS
